EP910PI-30T vs EP910PI-40 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910PI-30T disebabkan oleh Altera dan EP910PI-40 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EP910PI-40 EP910PI-40 - 24-Macrocell Classic EPLD, 43ns, PDIP-40 | Altera

EP910PI-40 - 24-Macrocell Classic EPLD, 43ns, PDIP-40 | Altera

EP910PI-40 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EP910PI-30T EP910PI-40
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Masa Terakhir Dibeli
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD —
Macrocells 24 —
Usable Gates 480 —
Dedicated Inputs 10 —
Propagation Delay (tPD) 30 ns 43 ns
Register (Clock-to-Output) Delay 20 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 4.75 V to 5.25 V (5 V nominal)
Technology CMOS, UV-erasable (windowed ceramic) —
Package Type 40-pin PDIP (ceramic windowed) —
Jenis Pemasangan Through-Hole Through-Hole
Suhu Operasi -40 C to +85 C (industrial) 0C to +70C (commercial)
Programming Altera Classic device programmer / MAX+PLUS II flow —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Lead-Free [DATA_NEEDED: lead-free status] —
Device Family — Classic EPLD
Part Number — EP910PI-40
Architecture — PAL-type macrocell, CMOS, UV-erasable
Number of Macrocells — 24
Number of Dedicated Inputs — 12
Number of I/O Lines — 24
External Clock Inputs — 2
Frekuensi Klock Maksimum — 25 MHz
Speed Grade — -40 (43 ns)
Kemasan — PDIP-40 (Plastic DIP, 40-pin)
Process Technology — CMOS (UV-erasable)
Programming Method — UV-erase + Altera programmer (legacy)
Programmable Polarity — Yes (user-configurable output)
Output Enable Control — Yes (per-pin three-state)

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