EPC2LC20EM vs EPC2L20 Comparación
Comparación detallada lado a lado de EPC2LC20EM por Intel y EPC2L20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2LC20EM | EPC2L20 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | Memory ICs |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,95 | $25,80 |
| Tipo de memoria | Serial Configuration Memory (EPC2 family) | Configuration PROM (non-volatile) |
| Density | 1.6 Mbit | — |
| Interfaz | Serial / Parallel configuration, JTAG ISP | Serial FPGA configuration + JTAG (IEEE 1149.1 / IEEE 1532) |
| Operating Voltage (Core) | 3.3 V | — |
| Programming Mode | In-system programmable via JTAG (IEEE 1149.1) | — |
| Package Type | PLCC-20 (plastic) | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Estado RoHS | [DATA_NEEDED: lead-free / RoHS classification] | RoHS Compliant (per IC Components listing) |
| Configuration Compatibility | Stratix, Cyclone, APEX, ACEX, FLEX, MAX, Excalibur, HardCopy | — |
| Data Retention | [DATA_NEEDED: minimum data-retention years] | — |
| Program/Erase Cycles | [DATA_NEEDED: minimum endurance cycles] | — |
| Access Time | [DATA_NEEDED: tOE / tAA in ns] | — |
| Tipo de montaje | Surface Mount (PLCC socket or solder) | Surface Mount (PLCC socket compatible) |
| Nivel MSL | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: MSL rating] |
| Manufacturer Family | EPC2 Enhanced Configuration Device | — |
| Tamaño de memoria | — | 1.6 Mbit |
| Organización de memoria | — | 8-bit byte |
| Programmability | — | In-system programmable via JTAG |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5.0 V (VCCSEL selectable) |
| Cascade Support | — | Yes - multi-device daisy chain |
| Boundary Scan | — | JTAG IEEE 1149.1 BST |
| Encapsulado | — | 20-pin PLCC (J-lead) |
| Process Technology | — | Low-power CMOS |
| Target FPGAs | — | APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, Stratix |