EPC2LC20EM vs EPC2L20 Comparaison
Comparaison détaillée côte à côte de EPC2LC20EM par Intel et EPC2L20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2LC20EM | EPC2L20 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | Memory ICs |
| Statut du cycle de vie | Actif | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,95 | $25,80 |
| Type de mémoire | Serial Configuration Memory (EPC2 family) | Configuration PROM (non-volatile) |
| Density | 1.6 Mbit | — |
| Interface | Serial / Parallel configuration, JTAG ISP | Serial FPGA configuration + JTAG (IEEE 1149.1 / IEEE 1532) |
| Operating Voltage (Core) | 3.3 V | — |
| Programming Mode | In-system programmable via JTAG (IEEE 1149.1) | — |
| Package Type | PLCC-20 (plastic) | — |
| Température de fonctionnement | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Statut RoHS | [DATA_NEEDED: lead-free / RoHS classification] | RoHS Compliant (per IC Components listing) |
| Configuration Compatibility | Stratix, Cyclone, APEX, ACEX, FLEX, MAX, Excalibur, HardCopy | — |
| Data Retention | [DATA_NEEDED: minimum data-retention years] | — |
| Program/Erase Cycles | [DATA_NEEDED: minimum endurance cycles] | — |
| Access Time | [DATA_NEEDED: tOE / tAA in ns] | — |
| Type de montage | Surface Mount (PLCC socket or solder) | Surface Mount (PLCC socket compatible) |
| Niveau MSL | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: MSL rating] |
| Manufacturer Family | EPC2 Enhanced Configuration Device | — |
| Taille de mémoire | — | 1.6 Mbit |
| Organisation de la mémoire | — | 8-bit byte |
| Programmability | — | In-system programmable via JTAG |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5.0 V (VCCSEL selectable) |
| Cascade Support | — | Yes - multi-device daisy chain |
| Boundary Scan | — | JTAG IEEE 1149.1 BST |
| Boîtier | — | 20-pin PLCC (J-lead) |
| Process Technology | — | Low-power CMOS |
| Target FPGAs | — | APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, Stratix |