EPC2LI20 vs EPC2L20 Comparación
Comparación detallada lado a lado de EPC2LI20 por Altera y EPC2L20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2LI20 | EPC2L20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,95 | $25,80 |
| Tamaño de memoria | 1.6 Mb (1,572,864 bits) | 1.6 Mbit |
| Tipo de memoria | Flash (in-system programmable) | Configuration PROM (non-volatile) |
| Programmable Type | In System Programmable (ISP) | — |
| Función | Configuration PROM for SRAM-based FPGAs | — |
| Supply Voltage - Operating | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) | — |
| Temperatura de funcionamiento | -40 C to +85 C (Industrial) | [DATA_NEEDED: operating temperature range] |
| Encapsulado / Carcasa | 20-PLCC (J-lead, 9x9 mm) | — |
| Tipo de montaje | Surface Mount (PLCC socket-compatible) | Surface Mount (PLCC socket compatible) |
| Configuration Interface | Serial or Byte-wide (parallel) | — |
| Decompression | On-chip (supports compressed bitstreams) | — |
| JTAG / ISP Interface | IEEE 1532 (TCK, TMS, TDI, TDO) | — |
| Multi-Device Support | Yes (daisy-chain configuration) | — |
| User-Accessible Memory | Yes (unused flash available to user logic) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | RoHS Compliant (per IC Components listing) |
| Nivel MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| Organización de memoria | — | 8-bit byte |
| Interfaz | — | Serial FPGA configuration + JTAG (IEEE 1149.1 / IEEE 1532) |
| Programmability | — | In-system programmable via JTAG |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5.0 V (VCCSEL selectable) |
| Cascade Support | — | Yes - multi-device daisy chain |
| Boundary Scan | — | JTAG IEEE 1149.1 BST |
| Encapsulado | — | 20-pin PLCC (J-lead) |
| Process Technology | — | Low-power CMOS |
| Target FPGAs | — | APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, Stratix |