EPF10K250EFC672-3 vs EPF10K250EFC672-2 Comparación
Comparación detallada lado a lado de EPF10K250EFC672-3 por Intel y EPF10K250EFC672-2 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPF10K250EFC672-3 | EPF10K250EFC672-2 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $99,50 | $108,00 |
| Product Type | FPGA (Field Programmable Gate Array) | — |
| Family | FLEX 10KE | FLEX 10KE |
| Maximum Typical Gates | 250,000 | — |
| Logic Elements (LEs) | 12,160 | — |
| Embedded Memory (EAB) | 655,360 bits (80 EABs x 2,048 bits each) | — |
| Logic Array Blocks (LABs) | 392 (8 LEs per LAB) | — |
| User I/O Pins | 470 | — |
| Core Supply Voltage | 2.5 V | 2.3 V (typical 2.5 V) |
| I/O Supply Voltage | MultiVolt: 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Speed Grade | -3 (fastest) | — |
| Temperature Grade | Commercial (0C to +70C) | — |
| Encapsulado | 672-ball FineLine BGA (FC) | 672-BGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch |
| Ball Pitch | 1.0 mm | — |
| Configuration Mode | JTAG (IEEE 1149.1) ISP / serial / parallel, external EPCx PROM | — |
| Process Technology | 0.25 um CMOS, 5-layer metal | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status - 672-FBGA part is non-RoHS per Fly-Wing listing] | Non-RoHS Compliant (per Fly-Wing listing) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | — | 12,480 |
| Typical Gates | — | 250,000 |
| Embedded Array Blocks (EABs) | — | 20 |
| Maximum User RAM Bits | — | 40,960 |
| User I/Os | — | 470 |
| Recuento de pines | — | 672 |
| Propagation Delay | — | 0.4 ns |
| Temperatura de funcionamiento | — | 0 C to +70 C (Commercial) |
| I/O Standard Support | — | 1.8 V, 2.5 V, 3.3 V (multi-volt I/O) |
| Logic Family | — | CMOS, SRAM-based |
| Configuration | — | SRAM, in-system programmable (ISP) via JTAG |
| Boundary Scan | — | IEEE 1149.1 (JTAG) compliant |