EPF10K250EFC672-3 vs EPF10K250EFC672-2 Comparaison
Comparaison détaillée côte à côte de EPF10K250EFC672-3 par Intel et EPF10K250EFC672-2 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K250EFC672-3 | EPF10K250EFC672-2 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $99,50 | $108,00 |
| Product Type | FPGA (Field Programmable Gate Array) | — |
| Family | FLEX 10KE | FLEX 10KE |
| Maximum Typical Gates | 250,000 | — |
| Logic Elements (LEs) | 12,160 | — |
| Embedded Memory (EAB) | 655,360 bits (80 EABs x 2,048 bits each) | — |
| Logic Array Blocks (LABs) | 392 (8 LEs per LAB) | — |
| User I/O Pins | 470 | — |
| Core Supply Voltage | 2.5 V | 2.3 V (typical 2.5 V) |
| I/O Supply Voltage | MultiVolt: 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Speed Grade | -3 (fastest) | — |
| Temperature Grade | Commercial (0C to +70C) | — |
| Boîtier | 672-ball FineLine BGA (FC) | 672-BGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch |
| Ball Pitch | 1.0 mm | — |
| Configuration Mode | JTAG (IEEE 1149.1) ISP / serial / parallel, external EPCx PROM | — |
| Process Technology | 0.25 um CMOS, 5-layer metal | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status - 672-FBGA part is non-RoHS per Fly-Wing listing] | Non-RoHS Compliant (per Fly-Wing listing) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | — | 12,480 |
| Typical Gates | — | 250,000 |
| Embedded Array Blocks (EABs) | — | 20 |
| Maximum User RAM Bits | — | 40,960 |
| User I/Os | — | 470 |
| Nombre de broches | — | 672 |
| Propagation Delay | — | 0.4 ns |
| Température de fonctionnement | — | 0 C to +70 C (Commercial) |
| I/O Standard Support | — | 1.8 V, 2.5 V, 3.3 V (multi-volt I/O) |
| Logic Family | — | CMOS, SRAM-based |
| Configuration | — | SRAM, in-system programmable (ISP) via JTAG |
| Boundary Scan | — | IEEE 1149.1 (JTAG) compliant |