EPM240M100C5N vs EPM240M100C4N Comparación
Comparación detallada lado a lado de EPM240M100C5N por Intel y EPM240M100C4N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM240M100C5N | EPM240M100C4N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $4,25 | $7,45 |
| Family | MAX II | — |
| Logic Elements | 240 | — |
| Macrocells | 192 | — |
| User I/Os | 80 | 80 |
| Propagation Delay (tPD) | 4.7 ns | — |
| User Flash Memory | 8 Kbits | 8 Kbit |
| Supply Voltage - Core | 1.8 V | 2.5 V / 3.3 V |
| Supply Voltage - I/O | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Temperatura de funcionamiento | -40 C to +125 C | -40 C to +125 C (industrial) |
| Encapsulado | 100-ball MBGA (Micro FBGA), 6 x 6 mm, 0.5 mm pitch | 100-pin Micro FineLine BGA (MBGA), 6 x 6 mm, 0.5 mm pitch |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Process Technology | 0.18 µm CMOS | — |
| Configuration Memory | On-chip Flash (non-volatile) | Non-volatile on-chip flash (instant-on) |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Estado RoHS | Compliant (lead-free) | Lead Free (per DigiChip spec sheet) |
| Logic Family | CMOS | CMOS |
| Series | — | MAX II |
| Device Family | — | EPM240 |
| Macro Cells | — | 192 |
| Propagation Delay (tPD) Max | — | 4.7 ns |
| Internal Operating Frequency | — | 247.5 MHz |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| Programmability | — | In-System Programmable via JTAG (IEEE 1149.1) |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells per LAB) |
| MultiTrack Interconnect | — | Yes |
| Hot Socketing | — | Yes |