EPM240M100C5N vs EPM240M100C4N 对比

详细并排对比 EPM240M100C5N 出自 Intel 和 EPM240M100C4N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Intel
EPM240M100C5N EPM240M100C5N - MAX II CPLD 192MC 80 I/O | Intel

EPM240M100C5N - MAX II CPLD 192MC 80 I/O | Intel

EPM240M100C5N ⚠ 最后一次采购

规格对比

参数 EPM240M100C5N EPM240M100C4N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 有效
库存状态 有库存 有库存
单价(USD) $4.25 $7.45
Family MAX II —
Logic Elements 240 —
Macrocells 192 —
User I/Os 80 80
Propagation Delay (tPD) 4.7 ns —
User Flash Memory 8 Kbits 8 Kbit
Supply Voltage - Core 1.8 V 2.5 V / 3.3 V
Supply Voltage - I/O 1.5 V / 1.8 V / 2.5 V / 3.3 V —
工作温度 -40 C to +125 C -40 C to +125 C (industrial)
封装 100-ball MBGA (Micro FBGA), 6 x 6 mm, 0.5 mm pitch 100-pin Micro FineLine BGA (MBGA), 6 x 6 mm, 0.5 mm pitch
安装类型 Surface Mount Surface Mount (BGA)
Process Technology 0.18 µm CMOS —
Configuration Memory On-chip Flash (non-volatile) Non-volatile on-chip flash (instant-on)
JTAG Support IEEE 1149.1 boundary-scan —
RoHS 状态 Compliant (lead-free) Lead Free (per DigiChip spec sheet)
Logic Family CMOS CMOS
Series — MAX II
Device Family — EPM240
Macro Cells — 192
Propagation Delay (tPD) Max — 4.7 ns
Internal Operating Frequency — 247.5 MHz
I/O Standards Supported — 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL
Programmability — In-System Programmable via JTAG (IEEE 1149.1)
Logic Array Blocks (LABs) — 4 (16 macrocells per LAB)
MultiTrack Interconnect — Yes
Hot Socketing — Yes

数据手册与资源

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