EPM5192AGC-15 vs EPM5192-1LC Comparación
Comparación detallada lado a lado de EPM5192AGC-15 por Altera y EPM5192-1LC por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192AGC-15 | EPM5192-1LC |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $27,80 | $19,40 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (typical for 192-macrocell MAX 5000) | — |
| Maximum User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Encapsulado | Ceramic Pin Grid Array (PGA) | 64-pin Ceramic J-Lead Chip Carrier (LC) |
| Programming Method | UV erase + EPROM program (via Altera programmer) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Estado RoHS | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] | Non-compliant (ceramic windowless package, lead-bearing termination) |
| Estado del ciclo de vida | Obsolete / Last Time Buy (per Altera legacy product list) | — |
| Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 3,750 |
| Logic Array Blocks (LABs) | — | 4 |
| User I/O Pins | — | 64 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Propagation Delay (tpd) | — | [DATA_NEEDED: -1 speed grade tpd in ns] |
| Tensión de alimentación | — | 5 V |
| Process Technology | — | UV EPROM, erasable windowless |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Tipo de montaje | — | Surface Mount |