EPM5192AGC-15 vs EPM5192-1LC 对比

详细并排对比 EPM5192AGC-15 出自 Altera 和 EPM5192-1LC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192AGC-15 EPM5192-1LC
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $27.80 $19.40
Product Type EPLD (Erasable Programmable Logic Device) —
Series MAX 5000 —
Macrocells 192 192
Logic Array Blocks 16 (typical for 192-macrocell MAX 5000) —
Maximum User I/O Pins 64 —
Dedicated Inputs 7 —
Total Inputs 72 —
Propagation Delay (tPD) 15 ns (pin-to-pin, -15 speed grade) —
Supply Voltage (VCC) 5 V —
Technology CMOS, UV-erasable EPROM —
封装 Ceramic Pin Grid Array (PGA) 64-pin Ceramic J-Lead Chip Carrier (LC)
Programming Method UV erase + EPROM program (via Altera programmer) —
工作温度 [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
RoHS 状态 [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] Non-compliant (ceramic windowless package, lead-bearing termination)
生命周期状态 Obsolete / Last Time Buy (per Altera legacy product list) —
Family — MAX 5000
Device Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 3,750
Logic Array Blocks (LABs) — 4
User I/O Pins — 64
Maximum Operating Frequency — 62.5 MHz
Propagation Delay (tpd) — [DATA_NEEDED: -1 speed grade tpd in ns]
电源电压 — 5 V
Process Technology — UV EPROM, erasable windowless
Programmable Interconnect — PIA (Programmable Interconnect Array)
JTAG Boundary Scan — IEEE 1149.1 compliant
安装类型 — Surface Mount

数据手册与资源

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