EPM5192AGC-15 vs EPM5192-1LC Comparaison
Comparaison détaillée côte à côte de EPM5192AGC-15 par Altera et EPM5192-1LC par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192AGC-15 | EPM5192-1LC |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $27,80 | $19,40 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (typical for 192-macrocell MAX 5000) | — |
| Maximum User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Boîtier | Ceramic Pin Grid Array (PGA) | 64-pin Ceramic J-Lead Chip Carrier (LC) |
| Programming Method | UV erase + EPROM program (via Altera programmer) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Statut RoHS | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] | Non-compliant (ceramic windowless package, lead-bearing termination) |
| Statut du cycle de vie | Obsolete / Last Time Buy (per Altera legacy product list) | — |
| Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 3,750 |
| Logic Array Blocks (LABs) | — | 4 |
| User I/O Pins | — | 64 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Propagation Delay (tpd) | — | [DATA_NEEDED: -1 speed grade tpd in ns] |
| Tension d'alimentation | — | 5 V |
| Process Technology | — | UV EPROM, erasable windowless |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Type de montage | — | Surface Mount |