EPM7160STC100-10N vs EPM7160STC100-10 Comparación
Comparación detallada lado a lado de EPM7160STC100-10N por Altera y EPM7160STC100-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7160STC100-10N - MAX 7000 CPLD, 160 Macrocells, TQFP-100 | Altera
EPM7160STC100-10N ObsoleteIntel
EPM7160STC100-10 - MAX 7000S CPLD, 160 Macrocells, 100-pin TQFP | Intel
EPM7160STC100-10 ⚠ Última compraComparación de especificaciones
| Parámetro | EPM7160STC100-10N | EPM7160STC100-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $15,95 | $15,90 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | — |
| User I/Os | 84 | 84 |
| Equivalent Gates | 3.2K | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Operating Frequency | 167 MHz max | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| I/O Voltage (VCCIO) | 3.0 V to 5.25 V (MultiVolt) | — |
| Logic Family | CMOS | — |
| Programmable Type | In-System Programmable (ISP) via JTAG | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Encapsulado | TQFP-100 (1 mm height, plastic) | 100-pin TQFP |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0 C to +70 C (commercial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| JTAG (IEEE 1149.1) | Yes | — |
| PCI Compliance | Yes (66 MHz) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Non-RoHS (legacy Altera part; -10N variant is RoHS) |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 160 |
| Usable Gates | — | 3,200 |
| Logic Elements | — | 160 macrocells / 10 Logic Array Blocks |
| Supply Voltage (VCC) | — | 5.0 V (4.75 V - 5.25 V) |
| Propagation Delay (tPD1) | — | 10 ns |
| Global Clock Setup Time | — | 6 ns |
| Internal Counter Frequency | — | 100 MHz |
| Technology | — | CMOS, EEPROM-based |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |