EPM7160STC100-10N vs EPM7160STC100-10 Comparaison
Comparaison détaillée côte à côte de EPM7160STC100-10N par Altera et EPM7160STC100-10 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7160STC100-10N - MAX 7000 CPLD, 160 Macrocells, TQFP-100 | Altera
EPM7160STC100-10N ObsoleteIntel
EPM7160STC100-10 - MAX 7000S CPLD, 160 Macrocells, 100-pin TQFP | Intel
EPM7160STC100-10 ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM7160STC100-10N | EPM7160STC100-10 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $15,95 | $15,90 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | — |
| User I/Os | 84 | 84 |
| Equivalent Gates | 3.2K | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Operating Frequency | 167 MHz max | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| I/O Voltage (VCCIO) | 3.0 V to 5.25 V (MultiVolt) | — |
| Logic Family | CMOS | — |
| Programmable Type | In-System Programmable (ISP) via JTAG | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Boîtier | TQFP-100 (1 mm height, plastic) | 100-pin TQFP |
| Température de fonctionnement | 0C to +70C (Commercial) | 0 C to +70 C (commercial) |
| Type de montage | Surface Mount | Surface Mount |
| JTAG (IEEE 1149.1) | Yes | — |
| PCI Compliance | Yes (66 MHz) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Non-RoHS (legacy Altera part; -10N variant is RoHS) |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 160 |
| Usable Gates | — | 3,200 |
| Logic Elements | — | 160 macrocells / 10 Logic Array Blocks |
| Supply Voltage (VCC) | — | 5.0 V (4.75 V - 5.25 V) |
| Propagation Delay (tPD1) | — | 10 ns |
| Global Clock Setup Time | — | 6 ns |
| Internal Counter Frequency | — | 100 MHz |
| Technology | — | CMOS, EEPROM-based |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |