EPM7160STC100-10N vs EPM7160STC100-10 对比

详细并排对比 EPM7160STC100-10N 出自 Altera 和 EPM7160STC100-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Intel
EPM7160STC100-10 EPM7160STC100-10 - MAX 7000S CPLD, 160 Macrocells, 100-pin TQFP | Intel

EPM7160STC100-10 - MAX 7000S CPLD, 160 Macrocells, 100-pin TQFP | Intel

EPM7160STC100-10 ⚠ 最后一次采购

规格对比

参数 EPM7160STC100-10N EPM7160STC100-10
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $15.95 $15.90
Family MAX 7000S MAX 7000S
Macrocells 160 —
User I/Os 84 84
Equivalent Gates 3.2K —
Propagation Delay (tPD) 10 ns —
Internal Operating Frequency 167 MHz max —
Supply Voltage (VCCINT) 4.75 V to 5.25 V —
I/O Voltage (VCCIO) 3.0 V to 5.25 V (MultiVolt) —
Logic Family CMOS —
Programmable Type In-System Programmable (ISP) via JTAG —
Configuration Memory EEPROM (non-volatile) —
封装 TQFP-100 (1 mm height, plastic) 100-pin TQFP
工作温度 0C to +70C (Commercial) 0 C to +70 C (commercial)
安装类型 Surface Mount Surface Mount
JTAG (IEEE 1149.1) Yes —
PCI Compliance Yes (66 MHz) —
RoHS 状态 [DATA_NEEDED: RoHS status] Non-RoHS (legacy Altera part; -10N variant is RoHS)
MSL 等级 [DATA_NEEDED: MSL level] —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 160
Usable Gates — 3,200
Logic Elements — 160 macrocells / 10 Logic Array Blocks
Supply Voltage (VCC) — 5.0 V (4.75 V - 5.25 V)
Propagation Delay (tPD1) — 10 ns
Global Clock Setup Time — 6 ns
Internal Counter Frequency — 100 MHz
Technology — CMOS, EEPROM-based
In-System Programmability — Yes (IEEE 1149.1 JTAG)

数据手册与资源

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