EPM9320LC84-15 vs EPM9320ALC84-20 Comparación
Comparación detallada lado a lado de EPM9320LC84-15 por Intel y EPM9320ALC84-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320LC84-15 | EPM9320ALC84-20 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,95 | $10,50 |
| Family | MAX 9000 | MAX 9000 |
| Series | EPM9320 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | — |
| Logic Array Blocks (LABs) | 20 | 16 |
| Propagation Delay (tPD) | 15 ns (max) | — |
| Frecuencia de reloj máxima | 117.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | In-system via IEEE 1149.1 JTAG |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | — |
| Encapsulado | 84-pin PLCC (Plastic Leaded Chip Carrier) | PLCC-84 |
| Tipo de montaje | Surface Mount | Surface Mount (PLCC socket compatible) |
| Temperatura de funcionamiento | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | [DATA_NEEDED: commercial or industrial grade] |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | — |
| Built-in Pull-up Resistors | Yes, on every I/O pin | — |
| Architecture Feature | Pin-locking across design iterations | — |
| Estado RoHS | [DATA_NEEDED: confirm from manufacturer] | [DATA_NEEDED: per Altera datasheet] |
| Maximum User I/Os | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Process Technology | — | 0.5 µm CMOS EEPROM |
| Tensión de alimentación | — | 5.0 V |
| Configuration Memory | — | Non-volatile EEPROM |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Design Software | — | MAX+PLUS II / Quartus II (legacy) |