EPM9320LC84-15 vs EPM9320ALC84-20 Comparison
Detailed side-by-side comparison of EPM9320LC84-15 by Intel and EPM9320ALC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320LC84-15 | EPM9320ALC84-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.95 | $10.50 |
| Family | MAX 9000 | MAX 9000 |
| Series | EPM9320 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | β |
| Logic Array Blocks (LABs) | 20 | 16 |
| Propagation Delay (tPD) | 15 ns (max) | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | β |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | In-system via IEEE 1149.1 JTAG |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | β |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) | PLCC-84 |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket compatible) |
| Operating Temperature | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | [DATA_NEEDED: commercial or industrial grade] |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | β |
| Built-in Pull-up Resistors | Yes, on every I/O pin | β |
| Architecture Feature | Pin-locking across design iterations | β |
| RoHS Status | [DATA_NEEDED: confirm from manufacturer] | [DATA_NEEDED: per Altera datasheet] |
| Maximum User I/Os | β | 212 |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Process Technology | β | 0.5 Β΅m CMOS EEPROM |
| Supply Voltage | β | 5.0 V |
| Configuration Memory | β | Non-volatile EEPROM |
| Boundary Scan | β | JTAG IEEE 1149.1 |
| Design Software | β | MAX+PLUS II / Quartus II (legacy) |