EPM9320LC84-20 vs EPM9320LI84-20N Comparación
Comparación detallada lado a lado de EPM9320LC84-20 por Altera y EPM9320LI84-20N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320LC84-20 | EPM9320LI84-20N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $9,75 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Logic Family | CMOS (EEPROM-based) | CMOS, EEPROM-based |
| Encapsulado | PLCC-84 (Plastic Leaded Chip Carrier) | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Pins | 84 | — |
| Propagation Delay (tPD) | 16 ns | 20 ns (speed grade -20) |
| Internal Counter Frequency | 118 MHz | — |
| Tensión de alimentación | 5.0 V | 5.0 V |
| Temperatura de funcionamiento | 0 C to 70 C | 0 C to +70 C (commercial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Dedicated Inputs | 4 (global clock / clear / OE) | — |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | Multiple Array MatriX (MAX) - third generation |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Usable Gates | — | 6,000 to 12,000 |
| User I/O Pins | — | 60 |
| Total Pins | — | 84 |
| Pin-to-Pin Delay | — | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | — | 118 MHz |
| Programming Interface | — | IEEE 1149.1 JTAG, in-system programmable |
| Process Technology | — | Advanced CMOS EEPROM |