EPM9320LC84-20 vs EPM9320LI84-20N Comparison
Detailed side-by-side comparison of EPM9320LC84-20 by Altera and EPM9320LI84-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320LC84-20 | EPM9320LI84-20N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $9.75 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| User I/Os | 60 | β |
| Logic Family | CMOS (EEPROM-based) | CMOS, EEPROM-based |
| Package | PLCC-84 (Plastic Leaded Chip Carrier) | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Pins | 84 | β |
| Propagation Delay (tPD) | 16 ns | 20 ns (speed grade -20) |
| Internal Counter Frequency | 118 MHz | β |
| Supply Voltage | 5.0 V | 5.0 V |
| Operating Temperature | 0 C to 70 C | 0 C to +70 C (commercial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | β |
| Dedicated Inputs | 4 (global clock / clear / OE) | β |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | Multiple Array MatriX (MAX) - third generation |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Usable Gates | β | 6,000 to 12,000 |
| User I/O Pins | β | 60 |
| Total Pins | β | 84 |
| Pin-to-Pin Delay | β | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | β | 118 MHz |
| Programming Interface | β | IEEE 1149.1 JTAG, in-system programmable |
| Process Technology | β | Advanced CMOS EEPROM |