EPM9320LC84-20 vs EPM9320LI84-20N 对比
详细并排对比 EPM9320LC84-20 出自 Altera 和 EPM9320LI84-20N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9320LC84-20 | EPM9320LI84-20N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.75 | $9.75 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Logic Family | CMOS (EEPROM-based) | CMOS, EEPROM-based |
| 封装 | PLCC-84 (Plastic Leaded Chip Carrier) | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Pins | 84 | — |
| Propagation Delay (tPD) | 16 ns | 20 ns (speed grade -20) |
| Internal Counter Frequency | 118 MHz | — |
| 电源电压 | 5.0 V | 5.0 V |
| 工作温度 | 0 C to 70 C | 0 C to +70 C (commercial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Dedicated Inputs | 4 (global clock / clear / OE) | — |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | Multiple Array MatriX (MAX) - third generation |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Usable Gates | — | 6,000 to 12,000 |
| User I/O Pins | — | 60 |
| Total Pins | — | 84 |
| Pin-to-Pin Delay | — | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | — | 118 MHz |
| Programming Interface | — | IEEE 1149.1 JTAG, in-system programmable |
| Process Technology | — | Advanced CMOS EEPROM |