EPM9560ARC208-10 vs EPM9560R1208-20 Comparación
Comparación detallada lado a lado de EPM9560ARC208-10 por Intel y EPM9560R1208-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560ARC208-10 | EPM9560R1208-20 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $22,40 |
| Device Family | MAX 9000A (Multiple Array MatriX) | — |
| Programmable Logic Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 gates | 6,000 |
| Macrocells | 560 macrocells | 560 |
| Logic Array Blocks | 35 LABs | 52 (typical for 560 macrocells) |
| User I/O Pins | 153 I/O | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | 20 ns |
| Internal Frequency | 144.9 MHz | — |
| Tensión de alimentación | 5.0 V | — |
| Logic Family | CMOS | — |
| Configuration Technology | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan (ISP) | — |
| Temperatura de funcionamiento | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Encapsulado | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad | R-1208 (BGA-style fine-pitch) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm via current distributor data] |
| Recuento de pines | 208 pins | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O | — | 212 |
| Maximum Frequency (fMAX) | — | 125 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Process Technology | — | CMOS EEPROM, third-generation MAX architecture |
| Architecture | — | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) |
| Boundary-Scan Test | — | JTAG IEEE Std. 1149.1 |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |