EPM9560ARC208-10 vs EPM9560R1208-20 对比

详细并排对比 EPM9560ARC208-10 出自 Intel 和 EPM9560R1208-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560ARC208-10 EPM9560R1208-20
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $0.00 $22.40
Device Family MAX 9000A (Multiple Array MatriX) —
Programmable Logic Type CPLD (Complex Programmable Logic Device) —
Usable Gates 12,000 gates 6,000
Macrocells 560 macrocells 560
Logic Array Blocks 35 LABs 52 (typical for 560 macrocells)
User I/O Pins 153 I/O —
Propagation Delay (tPD) 10 ns (speed grade -10) 20 ns
Internal Frequency 144.9 MHz —
电源电压 5.0 V —
Logic Family CMOS —
Configuration Technology EEPROM (non-volatile, in-system programmable) —
JTAG Interface IEEE 1149.1 boundary-scan (ISP) —
工作温度 0 C to +70 C (commercial) 0C to +70C (commercial)
封装 208-pin RQFP (PowerQuad Flat Pack) with exposed pad R-1208 (BGA-style fine-pitch)
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: confirm via current distributor data]
引脚数量 208 pins —
Family — MAX 9000
Device Type — CPLD (Complex Programmable Logic Device)
Maximum User I/O — 212
Maximum Frequency (fMAX) — 125 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Technology — CMOS EEPROM
In-System Programmability — Yes (IEEE 1149.1 JTAG)
Process Technology — CMOS EEPROM, third-generation MAX architecture
Architecture — Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA)
Boundary-Scan Test — JTAG IEEE Std. 1149.1
Configuration Memory — On-chip EEPROM (non-volatile)

数据手册与资源

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