EPM9560ARC208-10 vs EPM9560R1208-20 Comparaison
Comparaison détaillée côte à côte de EPM9560ARC208-10 par Intel et EPM9560R1208-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9560ARC208-10 | EPM9560R1208-20 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $22,40 |
| Device Family | MAX 9000A (Multiple Array MatriX) | — |
| Programmable Logic Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 gates | 6,000 |
| Macrocells | 560 macrocells | 560 |
| Logic Array Blocks | 35 LABs | 52 (typical for 560 macrocells) |
| User I/O Pins | 153 I/O | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | 20 ns |
| Internal Frequency | 144.9 MHz | — |
| Tension d'alimentation | 5.0 V | — |
| Logic Family | CMOS | — |
| Configuration Technology | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan (ISP) | — |
| Température de fonctionnement | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Boîtier | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad | R-1208 (BGA-style fine-pitch) |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm via current distributor data] |
| Nombre de broches | 208 pins | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O | — | 212 |
| Maximum Frequency (fMAX) | — | 125 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Process Technology | — | CMOS EEPROM, third-generation MAX architecture |
| Architecture | — | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) |
| Boundary-Scan Test | — | JTAG IEEE Std. 1149.1 |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |