H5ANAG6NCR-PBC vs H5ANAG6NBJR-RDC Comparación
Comparación detallada lado a lado de H5ANAG6NCR-PBC por SK hynix y H5ANAG6NBJR-RDC por SK hynix. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | H5ANAG6NCR-PBC | H5ANAG6NBJR-RDC |
|---|---|---|
| Marca | SK hynix | SK hynix |
| Categoría | Memory ICs | DRAM |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $70,20 | $9,60 |
| Tipo de memoria | DDR4 SDRAM | DDR4 SDRAM |
| Density | 16Gb (2GB) | 16 Gb |
| Organización de memoria | x16 (1G x 16) | — |
| Tensión de alimentación | 1.14 V to 1.26 V (nominal 1.2 V) | — |
| Transfer Rate | 3200 Mbps (family, per XNCR datasheet; PBC speed grade [DATA_NEEDED: exact speed grade Mbps]) | — |
| Encapsulado | FBGA-96 | FBGA (Ball Grid Array), surface mount |
| Number of Terminals | 96 balls | — |
| Temperatura de funcionamiento | 0C to 85C | [DATA_NEEDED: Operating Temperature Range] |
| Tipo de montaje | Surface Mount | Surface Mount |
| Auto Self-Refresh | Yes | — |
| Auto Precharge | Yes | — |
| Asynchronous Reset | Yes | — |
| Data Mask | Yes | — |
| Dynamic ODT | Yes | — |
| ZQ Calibration | Yes | — |
| CRC Function | Yes | — |
| Write Leveling | Yes | — |
| Estado RoHS | Compliant | [DATA_NEEDED: RoHS Status] |
| Maximum Standby Current | [DATA_NEEDED: maximum standby current for PBC speed grade] | — |
| Latencia CAS | [DATA_NEEDED: CAS latency for PBC speed grade] | — |
| Memory Organization | — | 16Gb x16 |
| Velocidad de datos | — | 2666 Mbps (speed grade -RDC) |
| Supply Voltage (VDD) | — | 1.2 V |
| Interfaz | — | Synchronous, double data rate |
| Clocking | — | Fully synchronous to both clock edges |
| Technology | — | CMOS |
| Standard | — | JEDEC DDR4 SDRAM |
| Application | — | Main memory |
| On-Die Termination (ODT) | — | Supported (DDR4 feature) |
| Bank Group Architecture | — | DDR4 bank groups (per JEDEC DDR4) |