P1022NXN2LFB vs P1013NXN2LFB Comparación
Comparación detallada lado a lado de P1022NXN2LFB por NXP Semiconductors y P1013NXN2LFB por NXP Semiconductors. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
NXP Semiconductors
P1022NXN2LFB - QorIQ Dual-Core 1.067 GHz SoC | NXP | Networking
P1022NXN2LFB ⚠ Última compraNXP Semiconductors
P1013NXN2LFB - QorIQ P1022 Power Arch SoC 1GHz | NXP
P1013NXN2LFB ⚠ Última compraComparación de especificaciones
| Parámetro | P1022NXN2LFB | P1013NXN2LFB |
|---|---|---|
| Marca | NXP Semiconductors | NXP Semiconductors |
| Categoría | Microcontrollers | Microcontrollers |
| Estado del ciclo de vida | Última compra | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $78,40 | $32,85 |
| Architecture | Power Architecture e500 dual-core (RISC, 32-bit) | — |
| Clock Speed (Core) | 1.067 GHz | — |
| Platform Version | 1067/533/667 ET NE r1.1 | — |
| Core Count | 2 | — |
| Package Type | TEPBGA-689 (Plastic, halogen-free, RoHS-compliant) | — |
| Package Dimensions | 31 x 31 mm, 2.23 mm height | — |
| Recuento de pines | 689 | — |
| Temperatura de funcionamiento | -40 °C to +125 °C (industrial) | -40C to +125C (junction) |
| Tensión de alimentación | 3.13 V to 3.47 V | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Memory Controller | DDR2/DDR3 with ECC support, up to 32-bit | DDR2/DDR3 with ECC, 64-bit data bus |
| Ethernet MACs | 3 x 10/100/1000 Mbps Gigabit | 3 x 10/100/1000 (2x SGMII/HS SerDes, 1x RGMII) |
| PCIe Interfaces | 3 x PCIe Gen1 | — |
| USB | USB 2.0 host/device | 1 x USB 2.0 with integrated PHY |
| Display Controller | 32-bit LCD controller | — |
| Security Engine | Integrated (symmetric/asymmetric crypto acceleration) | — |
| RoHS Compliance | Yes (halogen-free) | — |
| Tipo de montaje | Surface Mount (BGA, requires thermal via array under die) | Surface Mount (BGA) |
| Family | — | QorIQ P1022 (P1 series) |
| Core Architecture | — | 32-bit Power Architecture e500v2 |
| Number of Cores | — | 1 |
| Core Frequency | — | 1.067 GHz |
| L1 Cache (per core) | — | 32 KB instruction + 32 KB data |
| L2 Cache | — | 256 KB platform cache |
| PCI Express | — | 2 x PCIe Gen 1.1 (x4 / x1) |
| Other Interfaces | — | eSDHC, eSPI, I2C, UART, eLBC, LCD controller |
| Encapsulado | — | 689-ball TEPBGA II (31 mm x 31 mm) |
| Process | — | 45 nm SOI |
| Security | — | SEC 4.0 (optional crypto accelerator) on die variant |
| Estado RoHS | — | Compliant (Pb-free ball finish) |