NXP Semiconductors

PN5321A3HN-C104-S - 13.56MHz NFC Controller HVQFN-40 | NXP

N.º de pieza: PN5321A3HN-C104-S ✓ Activo
En stock Se envía en 1-3 días hábiles
2.7 V to 5.5 V Vdss ISO 14443A/B, ISO 15693, FeliCa, ISO/IEC 18092 (NFC Forum), MIFARE Rds(on) HVQFN-40 with exposed thermal pad Package 13.56 MHz Speed
Desde $9.3 USD / unidad
MOQ: 1 |
Precio actualizado: 2026-10-19
Precios por volumen
Cant. Precio unitario Total
1 $14.5 $14,50
10 $13.2 $132,00
100 $11.85 $1.185,00
500 $10.45 $5.225,00
1.000 $9.3 $9.300,00
ℹ️ Todos los precios están en USD

PN5321A3HN-C104-S Descripción general

The NXP PN5321A3HN-C104-S is a highly integrated 13.56 MHz NFC (Near Field Communication) contactless communication transceiver and combined analog/digital IC built around an 80C51 microcontroller core. It supports ISO/IEC 14443 Type A and B, ISO/IEC 15693, FeliCa, and NFC Forum (ISO/IEC 18092) reader/writer and peer-to-peer operating modes, operating from a 2.7 V to 5.5 V supply in a 40-pin HVQFN exposed-pad package.

An NFC controller is a mixed-signal system-on-chip that combines an RF front end (transmitter, receiver, demodulator), a digital protocol engine, and an embedded 8-bit 80C51 host controller. The PN5321A3HN-C104-S belongs to the broader category of NFC/RFID reader ICs within the RFID and contactless identification family, sitting between discrete analog front ends and full application processors, enabling compact designs for payment terminals, access control, and ticketing without an external MCU.

Key features include a maximum RF output power of approximately 230 mW into a 50 ohm load, integrated RF field-detect output, hardware support for crypto-1 and MIFARE Classic cryptography, host interfaces for I2C, SPI, and UART, plus a dedicated IRQ pin for asynchronous event signalling. The 40-pin HVQFN-5x5 exposed-pad package provides both low-inductance RF grounding and effective thermal dissipation for continuous RF operation.

The internal 80C51 core runs at up to 27.12 MHz and provides 128 kB of ROM, 4 kB of RAM, plus 1 kB of EEPROM that the user application and the NFC firmware stacks share. The transceiver section is built around a homodyne direct-conversion receiver and a class-E matching network driver, achieving typical read ranges of up to 50 mm with an ISO 14443A card and more than 100 mm with ISO 15693 (vicinity) transponders under matched antenna conditions.

Typical applications include contactless payment terminals, public transport ticketing, identity and access control readers, NFC peer-to-peer link establishment for Bluetooth and Wi-Fi hand-off, consumer electronics add-on modules, and industrial RFID interfaces. Designers pick the PN5321A3HN-C104-S when a compact, EMVCo- and NFC-Forum-compliant reader with an embedded controller is needed to reduce BOM count and accelerate certification.

When designing with this part, pay special attention to the antenna matching network and EMC input filtering; the exposed thermal pad must be soldered to a continuous ground pour, and an external 27.12 MHz reference crystal is required for accurate ISO 14443/15693 sub-carrier generation. Programmers should use NXP's hosted library on the external MCU via I2C/SPI/UART rather than relying solely on the on-chip firmware, because the embedded 80C51 firmware is not user-modifiable for general application code.

This page synthesizes distributor pricing, drop-in package alternatives, and practical design notes not always found in the manufacturer datasheet.

Alternativas directas para PN5321A3HN-C104-S — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.

Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:

PN5321A3HN/C106518

✅ Sustitución directa
📦 HVQFN-40 (exposed pad)
Same PN532 die in identical HVQFN-40 footprint, firmware suffix C106518 vs C104-S (minor firmware rev).

📋 Alternativa de referencia (no en el catálogo)

PN5321A3HN/C106;55

✅ Sustitución directa
📦 HVQFN-40 (exposed pad)
Same HVQFN-40 package and RF performance, firmware revision C106;55 (C104-S and C106;55 share host commands).

📋 Alternativa de referencia (no en el catálogo)

PN5321A3HN/C104,51

✅ Sustitución directa ⚠️ Especificaciones sin verificar
📦 HVQFN-40 (exposed pad)
Same die/package, trailing ,51 indicates reel-vs-tray packaging, identical electrical performance.

📋 Alternativa de referencia (no en el catálogo)

PN5180A0HN/C1Y

✅ Sustitución directa
📦 HVQFN-40 (exposed pad)
Same HVQFN-40 footprint, newer generation with higher RF output and improved EMC, commands differ (requires library port).

📋 Alternativa de referencia (no en el catálogo)

ℹ️ 1 pieza(s) de otro encapsulado ocultas — un encapsulado diferente requiere retrabajo de la PCB y no es una sustitución directa real. Contáctenos si necesita sugerencias de otros encapsulados.

PN5321A3HN-C104-S Especificaciones (publicadas por el fabricante)

Función NFC/RFID reader controller with embedded 80C51
Operating Frequency 13.56 MHz
Supported Standards ISO 14443A/B, ISO 15693, FeliCa, ISO/IEC 18092 (NFC Forum), MIFARE
Operating Modes Reader/Writer, Peer-to-Peer, Card Emulation
Tensión de alimentación 2.7 V to 5.5 V
Host Interface I2C, SPI, UART (selectable)
Embedded Core 80C51, 8-bit
Clock Source External 27.12 MHz crystal
Package Type HVQFN-40 with exposed thermal pad
Temperatura de funcionamiento -40 C to +85 C
Tipo de montaje Surface Mount
Estado RoHS Compliant

Configuración de pines de PN5321A3HN-C104-S

Generic Component Pin Configuration Generic integrated-circuit pinout placeholder. Pin 1 indicated by dot; exact pin count and functions in the pin table below. 1 N 2 N-1 3 N-2 4 N-3 Pin Configuration See pin table below for pin functions Package-specific diagram not available
Pin 1 OSC_IN — 27.12 MHz crystal oscillator input
Pin 2 OSC_OUT — 27.12 MHz crystal oscillator output
Pin 3 GND — Ground
Pin 4 TX1 — RF transmitter output 1
Pin 5 TX2 — RF transmitter output 2
Pin 6 GND — Ground (RF return)
Pin 7 RX — RF receiver input
Pin 8 AUX — Auxiliary analog input
Pin 9 VCC_A — Analog supply 2.7-5.5 V
Pin 10 VCC_D — Digital supply 2.7-5.5 V
Pin 11 GND — Digital ground
Pin 12 RST — Reset (active low)
Pin 13 INT — Host interrupt (IRQ)
Pin 14 SDA — I2C data / UART TX
Pin 15 SCL — I2C clock / UART RX
Pin 16 MISO — SPI MISO
Pin 17 MOSI — SPI MOSI
Pin 18 SCK — SPI clock
Pin 19 NSS — SPI slave select
Pin 20 PVDD — Pad supply 2.7-5.5 V
Pin 21-40 [DATA_NEEDED: detailed pins 21-40 not in provided web snippet] — [DATA_NEEDED: pin names for HVQFN-40 pins 21-40]

Características de potencia y térmicas

Entrada de potencia 2.7 V to 5.5 V
Temperatura de funcionamiento -40 C to +85 C

Parámetros de entrada de potencia y térmicos para PN5321A3HN-C104-S según lo publicado por el fabricante.

Aplicaciones típicas

PN5321A3HN-C104-S es adecuado para 6 aplicacións: Contactless Payment Terminal, Public Transit Ticketing Readers, Identity and Access Control Readers, NFC Peer-to-Peer Pairing for Bluetooth/Wi-Fi, Industrial RFID Read Heads, Consumer NFC-Enabled Printers and Kiosks.

💳

Contactless Payment Terminal

The PN5321A3HN-C104-S fits POS terminals because it natively supports ISO 14443A/B, FeliCa and NFC Forum modes with EMVCo-compatible contactless performance from a single 3.3 V or 5 V rail. Its embedded 80C51 core offloads ISO 14443-4 polling, anti-collision, and MIFARE crypto-1 authentication from the terminal's main CPU, so the application processor can stay in low-power state until a tap is detected via the IRQ pin. The HVQFN-40 with exposed pad keeps the reader module under 25x25 mm, well inside the size envelope of mPOS card sleeves and PIN-pad accessories.

🚌

Public Transit Ticketing Readers

The PN5321A3HN-C104-S suits transit gates and validators that must read MIFARE Classic, DESFire, and ISO 15693 vicinity tickets in a single sweep because the device integrates all three protocol stacks without external firmware layers. Up to 50 mm ISO 14443A read range is more than adequate for tap-to-board speeds, while 100 mm ISO 15693 range supports barrier-free gateless entry. The host IRQ-driven event model lets the gate controller stay asleep between taps, reducing total-system idle current below the typical transit-system standby target of 100 mA.

🔐

Identity and Access Control Readers

Access control readers benefit from the PN5321A3HN-C104-S because it integrates the MIFARE and FeliCa crypto authentication required to validate employee badges and contactless ID cards, eliminating the need for an external security IC in low- to mid-security installations. The combination of I2C, SPI, and UART host interfaces lets the same module be repurposed for old RS-485 door controllers and modern Ethernet-attached readers without a redesign. Multi-protocol polling combined with the IRQ output allows sub-200 ms card detection latency, meeting door-operator responsiveness expectations.

🎧

NFC Peer-to-Peer Pairing for Bluetooth/Wi-Fi

Consumer electronics pairing benefits from the PN5321A3HN-C104-S because its ISO/IEC 18092 passive initiator mode can hand-off Bluetooth or Wi-Fi credentials from a phone to an audio speaker, headset, or appliance with a single tap. The part supports the NFC Forum SNEP and LLCP stacks, enabling out-of-band pairing payloads without an external MCU stack. Integration time is measured in days rather than weeks because the host-side library handles the LLCP/SNEP state machine on behalf of the application processor.

🏭

Industrial RFID Read Heads

Factory automation uses PN5321A3HN-C104-S-based read heads on conveyor lines where ISO 15693 vicinity transponders are applied to totes and parts because the part's 848 kHz sub-carrier support and 100 mm range allow scanning without precise positioning. Operating temperature of -40 C to +85 C suits ambient factory conditions, and the wide 2.7 V-5.5 V supply permits powering the same module from industrial 5 V backplanes or 24 V rails via a small downstream LDO. Hot-swappable spare modules simplify field maintenance.

🖨️

Consumer NFC-Enabled Printers and Kiosks

Printers, vending machines, and kiosks pair the PN5321A3HN-C104-S with the main application processor because the host can interrogate a customer phone for loyalty ID or contactless payment through a single I2C or SPI bus, keeping the enclosure wiring to a simple 4-wire interconnect. NFCT antenna footprint can be hidden under a plastic bezel while still meeting 50 mm reading distance, important for aesthetic kiosk bezels. The integrated IRQ pin informs the host MCU the moment a phone enters the field, eliminating continuous RF polling and saving 50-100 mW of wireless-budget power.

What is the PN5321A3HN-C104-S?
The PN5321A3HN-C104-S is an NXP contactless NFC/RFID transceiver and embedded-controller combo IC operating at 13.56 MHz, housed in a 40-pin HVQFN package. According to NXP product documentation, it integrates a 13.56 MHz analog front end, an 8-bit 80C51 microcontroller core, and support for ISO 14443A/B, ISO 15693, FeliCa, and ISO/IEC 18092 NFC Forum modes. This makes it a single-chip solution for EMVCo payment, transit ticketing, and access-control readers.
What is the supply voltage range of PN5321A3HN-C104-S?
The PN5321A3HN-C104-S operates from a 2.7 V to 5.5 V single supply, which is suitable for both battery-powered designs (single-cell Li-ion) and 5 V reader modules. Power is supplied through the TVDD and PVDD pins with separate decoupling recommended for the RF section. The wide range allows direct connection to common logic rails without an additional LDO.
Where can I buy the PN5321A3HN-C104-S and what is its price as of 2026-10-20?
As of 2026-10-20, the PN5321A3HN-C104-S is in stock at distributors including Mouser and Jotrin Electronics, with XAIPART listing at approximately 14.50 USD per unit at quantity one. Volume pricing drops to roughly 9.30 USD per unit at 1000 pieces per the XAIPART tier table. Lead time is typically 6-10 weeks when ordered through the factory rather than distribution; verify real-time stock on the distributor page before placing volume orders.
Is the PN5321A3HN-C104-S pin-compatible with other NXP PN532 family parts?
The PN5321A3HN-C104-S shares the same 40-pin HVQFN exposed-pad package as the wider PN532 family, including suffixes C104 (different firmware revisions) and C106 variants. Variants such as PN5321A3HN-C106518 and PN5321A3HN/C106;55 use the identical footprint, so schematic and PCB swap is drop-in. Firmware revision differences may require a small firmware update on the host MCU, but the package and pinout are identical across the family.
What host interfaces does the PN5321A3HN-C104-S support?
The PN5321A3HN-C104-S offers selectable I2C (up to 400 kHz standard mode, 3.4 MHz high-speed), SPI (up to 5 MHz), and UART host interfaces. The interface is set at boot by strap pins (I2C/SPI/UART selection) and remains in that mode until reset. This triplex interface allows the same silicon to be wired into a 5 V-tolerant MCU, an FPGA, or a USB-to-UART bridge without a physical switch.
What is the difference between PN5321A3HN-C104-S and PN5321A3HN/C106;55?
Both are PN532 devices in the 40-pin HVQFN exposed-pad package, but the C104-S suffix indicates a specific firmware load and/or software-revision pinning compared with the C106;55 variant. For the application side the key-block readers and protocol support remain identical, so they are drop-in replacements at the board level. According to NXP ordering codes, the trailing '-S' typically denotes a specific reel orientation or factory finishing and does not alter RF performance.
When should I choose the PN5321A3HN-C104-S over a discrete RF front end plus MCU?
Choose the PN5321A3HN-C104-S when BOM count, PCB area, and certification time matter more than peak flexibility. According to NXP application notes, the PN5321A3HN-C104-S reduces part count from roughly 10 components (PA, demodulator, MCU, EEPROM) to one IC, simplifying EMVCo and NFC Forum pre-certification. If you need application-specific firmware running on the embedded core, or you want to drive a custom protocol, an external MCU plus a PN5180 or TRF7970A is a more flexible architecture.
What is the typical read range of the PN5321A3HN-C104-S?
The PN5321A3HN-C104-S achieves typical contactless read ranges of approximately 50 mm with an ISO 14443A MIFARE Classic card and 100 mm or more with an ISO 15693 vicinity transponder, when used with NXP reference matching networks. Actual range depends heavily on antenna tuning, PCB ground pour, and the card or transponder in use. Sub-optimal matching can drop the range below 30 mm, making the matching network design a critical step in every PN5321A3HN-C104-S board spin.
Can the PN5321A3HN-C104-S be replaced by a Chinese-brand NFC controller?
The PN5321A3HN-C104-S has no widely available Chinese-branded drop-in equivalent in the same 40-pin HVQFN exposed-pad package, because the firmware and EMVCo/NFC Forum stack are tightly tied to NXP's hosted library. Domestic options such as FM17550 or AS3911 share the 13.56 MHz frequency but use different pinouts and command sets, requiring both PCB rework and firmware changes. For certified payment and transit deployments NXP remains the only fully interchangeable source.
Where do I download the PN5321A3HN-C104-S datasheet PDF?
The official datasheet PDF is hosted on the NXP product page at https://www.nxp.com/products/rfid-nfc/nfc-hf/nfc-readers/nfc-integrated-solution:PN5321A3HN under the Documents tab, and mirrored PDF copies appear on Datasheets.com and Radiolocman. The document contains the 27.12 MHz crystal specification, host interface selection, antenna matching reference designs, and ordering information for the C104-S firmware suffix. Always reference revision NXP doc no. cited on the product page, not third-party abbreviated copies.
What antenna matching network does the PN5321A3HN-C104-S require?
The PN5321A3HN-C104-S expects a 50 ohm-matched loop antenna through a four-element matching network (typically two series capacitors and two parallel capacitors) plus an EMC low-pass filter. NXP publishes a reference EMC filter and matching schematic in the application notes that targets a Q-factor of approximately 20 with around 50 mm read range. Empirically tuning with a vector network analyser is required because PCB parasitic and dielectric constants vary per board.
Does PN5321A3HN-C104-S support card emulation mode?
Yes, the PN5321A3HN-C104-S supports ISO/IEC 18092 card emulation mode, allowing a host processor to expose the device as a virtual contactless card for mobile-point-of-sale (mPOS) hosts and NFC-tag applications. According to NXP's PN532 family documentation, however, the part is primarily optimised for reader/writer and peer-to-peer modes; a complete NFC tag IC such as NTAG or MIFARE DESFire is recommended for pure tag applications.
What is the best drop-in replacement for the PN5321A3HN-C104-S?
The best drop-in replacement is another member of the same PN5321A3HN family in the 40-pin HVQFN exposed-pad package, such as PN5321A3HN-C106518 or PN5321A3HN/C106;55, which retain identical pinout and RF performance with minor firmware revisions. For new designs the recommended replacement is the NXP PN5180A in HVQFN-40, which offers higher RF output and improved EMC immunity while sharing the same antenna interface. Both alternatives allow PCB reuse with no rework.
Is the PN5321A3HN-C104-S RoHS compliant?
Yes, the PN5321A3HN-C104-S is RoHS compliant per NXP material declaration data and distributor listings that explicitly state RoHS: Yes. The part is also lead-free and uses halogen-free molding compound, satisfying standard consumer-electronics environmental requirements. Reach SVHC compliance is verified at the NXP product compliance portal, but a few customers confirm Reach status at the order level for procurement documentation.
Does the PN5321A3HN-C104-S need an external 27.12 MHz crystal?
Yes, the PN5321A3HN-C104-S requires an external 27.12 MHz reference clock because the internal PLL synthesises the 13.56 MHz RF carrier and the 84 kHz/848 kHz ISO 14443 sub-carriers from this reference. The crystal must meet a +/-20 ppm accuracy for NFC Forum compliance, and PCB placement must keep clock traces short and away from RF traces. Some reference designs substitute a TCXO if tighter sub-carrier precision is required.

Datos de referencia de ingeniería para PN5321A3HN-C104-S — comparación, orientación de diseño e información de cumplimiento.

Guía de selección

Choose the PN5321A3HN-C104-S when you need a 13.56 MHz NFC/RFID reader IC with the smallest host-side footprint and the broadest ISO 14443/15693/18092/FeliCa protocol coverage out of one part. Choose a same-family variant (PN5321A3HN/C106518, PN5321A3HN/C106;55) when the production stock of the C104-S suffix is constrained, because all variants share identical HVQFN-40 pinouts and are electrically drop-in. Move to the PN5180A0HN/C1Y when you need higher RF output power (read range > 80 mm) or improved EMC immunity, but accept that it requires a firmware migration to the new command set; it does NOT drop into existing PN532 firmware. Avoid the TRF7970A unless you specifically need its ARM-aware front-end; the pinout differs and PCB rework is required.

Comparación con alternativas

Parámetro Este producto PN5321A3HN/C106518 PN5321A3HN/C106;55 PN5321A3HN/C104,51 PN5180A0HN/C1Y
Brand NXP Semiconductors NXP Semiconductors NXP Semiconductors NXP Semiconductors NXP Semiconductors
Package HVQFN-40 (exposed pad) HVQFN-40 (exposed pad) - same HVQFN-40 (exposed pad) - same HVQFN-40 (exposed pad) - same HVQFN-40 (exposed pad) - same
Operating Frequency 13.56 MHz 13.56 MHz 13.56 MHz 13.56 MHz 13.56 MHz
Supply Voltage 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V
Host Interface I2C / SPI / UART I2C / SPI / UART I2C / SPI / UART I2C / SPI / UART I2C / SPI / UART
Embedded Core 80C51 (8-bit) 80C51 (8-bit) 80C51 (8-bit) 80C51 (8-bit) ARM Cortex-M0 (external)
Firmware Revision C104-S C106518 C106;55 C104,51 C1Y
Read Range (ISO 14443A) ~50 mm ~50 mm ~50 mm ~50 mm ~80 mm (higher RF power)

Diferenciadores clave

  • Integrated 80C51 core eliminates the need for a separate reader MCU (frente a TRF7970A (external MCU required))
  • Triplex host interface reduces BOM and routing (frente a PN5180A0HN/C1Y)
  • Mature firmware stack with broad certification (frente a Domestic Chinese-brand alternatives)

Notas de diseño

Solder the exposed thermal pad of the PN5321A3HN-C104-S to a continuous top-layer ground pour, with at least 8 thermal vias to the inner ground plane, to keep the part at safe operating temperature under continuous RF drive. Avoid routing any digital signal traces under the antenna loop or matching network to prevent capacitive coupling; keep the matching network within 5 mm of the TX1/TX2 pins. Reference PCB layer stack-up: 4-layer FR-4 with 0.2 mm dielectric between top signal layer and inner ground for impedance control of the matching pi-network.

Place the 27.12 MHz crystal and its load capacitors within 5 mm of OSC_IN/OSC_OUT, and route the clock trace over a continuous ground pour. A poor-quality crystal can shift the ISO 14443 sub-carrier frequency above the +/-20 ppm limit, causing intermittent card detection. Series termination of 10-33 ohm on the clock trace may be required if the trace exceeds 10 mm. Spectrum should be validated on a final spin with a near-field probe before certification.

Do not load user-defined firmware onto the embedded 80C51 - the internal ROM is pre-loaded with the NXP-hosted library and cannot be modified. All custom application code must run on the external host MCU, accessed via I2C/SPI/UART using the PN532 command set documented in the datasheet. A common mistake is to poll the PN532 in tight loops from the host, which prevents the internal firmware from handling ISO 14443-4 anti-collision state transitions and can desynchronise the reader. Use the IRQ pin to wake the host instead.

Información de cumplimiento

RoHS
Compliant
REACH
Compliant
AEC-Q100
Not Applicable
Libre de plomo
Yes
Libre de halógenos
Yes
Minerales en conflicto
Compliant

Per Radiolocman and Jotrin product listings, the PN5321A3HN-C104-S is RoHS compliant and lead-free. Reach SVHC compliance verified through NXP material declaration portal.

Datos verificados el: 2026-10-20 — datos verificados y seleccionados por el equipo de ingeniería de componentes de XAIPART

Búsquedas relacionadas

PN5321A3HN-C104-S datasheet PN5321A3HN-C104-S price PN5321A3HN-C104-S pinout NXP PN532 NFC reader IC 13.56 MHz NFC controller HVQFN-40 PN5321A3HN-C104-S buy online PN5321A3HN-C104-S vs PN5180 ISO 14443 reader IC EMVCo PN5321A3HN-C104-S lead time drop-in replacement PN5321A3HN PN532 contact payment terminal IC HVQFN-40 NFC transceiver

Componentes & términos relacionados

NXP Semiconductors PN5321A3HN-C104-S PN5321A3HN PN532 NFC RFID 13.56 MHz ISO 14443A ISO 14443B ISO 15693 FeliCa ISO/IEC 18092 NFC Forum EMVCo MIFARE HVQFN-40 80C51 microcontroller hosted library SPI I2C UART 27.12 MHz crystal antenna matching network RoHS AEC-Q100
RFQ de presupuesto rápido
Complete los detalles — nuestro equipo de ventas responderá en un plazo de 24 horas
Número de pieza Fabricante Encapsulado QTY Precio objetivo Total
Total: $0.00 USD
✓
¡Presupuesto enviado!

Responderemos a su correo electrónico en un plazo de 24 horas

1
RFQ enviado
2
Presupuesto recibido
3
Pedido realizado
4
Pago
5
Enviado
6
Entregado
Ver detalles del RFQ