EP910PC-35 - 35ns 24-Macrocell EPLD | Altera | Classic EPLD
Référence : EP910PC-35 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $28.2 | $28,20 |
| 10 | $22.5 | $225,00 |
| 100 | $16.8 | $1 680,00 |
| 500 | $12.4 | $6 200,00 |
| 1 000 | $8.7 | $8 700,00 |
EP910PC-35 Présentation
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device from the pre-FPGA era, providing PAL-type sum-of-products logic with on-chip macrocells, a programmable AND/OR array, and reconfigurable I/O architecture. EPLDs sit in the programmable logic hierarchy between simple PAL/GAL devices and modern FPGAs, and the EP910 family specifically targets designs that need higher density and I/O count than 22V10-class devices while avoiding the complexity of SRAM-based FPGAs. The EP910PC-35 is the UV-erasable/OTP plastic-DIP variant of the EP910 family.
Key features include 24 macrocells with 24 I/O pins, 12 dedicated inputs giving 36 total inputs, 240 product terms distributed across the AND-array, and 35 ns typical pin-to-pin logic delay. The PAL-type architecture with buried macrocell registers, combined with CMOS technology, provides low power consumption and high noise immunity. The device operates from a single 5V supply and is in-system programmable via Altera's classic A+PLUS or MAX+PLUS development tools.
Architecturally, the EP910 family combines a global interconnect scheme with per-macrocell product-term allocation, allowing wide combinational and registered logic functions without the routing congestion of older PALs. Macrocell flip-flops can be configured as D, T, JK, or SR, with selectable clock polarity and asynchronous clear/preset — giving designers flexibility comparable to early 1990s PLDs.
Typical applications include address decoding and bus interface logic in 5V embedded systems, replacement of multiple 22V10 / 16L8 PALs in industrial controllers, glue logic in legacy telecom backplanes, and prototyping or low-volume production where FPGAs are over-specified. The plastic DIP package simplifies hand-soldering and rework on through-hole boards.
When designing with this device, ensure your programming tool supports the EP910 family — A+PLUS or MAX+PLUS legacy software is required. Note that plastic DIP packages are not windowed for UV erasure; use ceramic windowed CerDIP variants (EP910DC-35) during development and plastic for production. Decoupling: place a 0.1 uF capacitor on each VCC pin and minimize high-current switching near the device.
This page synthesizes distributor pricing, drop-in same-family EPLD alternatives (EP910PC-30, EP910PC-25), cross-reference compatibility information, and practical design notes that complement the manufacturer datasheet for legacy designs.
Alternatives de remplacement direct pour EP910PC-35 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP910PC-35 (même facteur de forme et même empreinte) — différant par Package, Programming Method, Supply Voltage (VCC), Technology, Usable Gates.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP910PC-30
✅ Remplacement direct✓ En stock
$6.5 / unité
Voir la fiche technique →EP910PC-25
✅ Remplacement direct✓ En stock
$16.92 / unité
Voir la fiche technique →EP910DC-35
✅ Remplacement direct✓ En stock
$10.95 / unité
Voir la fiche technique →EP910IPC-35
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EP910PC-40
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EP610PC-25
✅ Remplacement direct✓ En stock
$9.75 / unité
Voir la fiche technique →EP910PC-35 Valeurs maximales et caractéristiques électriques
| Family | Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 24 |
| I/O Pins | 24 |
| Dedicated Inputs | 12 |
| Total Inputs | 36 |
| Product Terms | 240 |
| Propagation Delay (tPD) | 35 ns |
| Maximum Counter Frequency | 37 MHz |
| Internal Performance Frequency | 100 MHz |
| Technology | CMOS, UV-erasable/OTP |
| Tension d'alimentation | 5 V |
| Boîtier | 40-pin PDIP (Plastic DIP) |
| Type de montage | Through-Hole |
| Architecture | PAL-type sum-of-products, AND/OR array |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools |
Configuration des broches de EP910PC-35
| Broche 1 | I/O — Macrocells 1-24 I/O pins (programmable input/output/bi-directional) |
| Broche 2 | I/O — Macrocells 1-24 I/O pins |
| Broche 3 | I/O — Macrocells 1-24 I/O pins |
| Broche 4 | I/O — Macrocells 1-24 I/O pins |
| Broche 5 | I/O — Macrocells 1-24 I/O pins |
| Broche 6 | I/O — Macrocells 1-24 I/O pins |
| Broche 7 | I/O — Macrocells 1-24 I/O pins |
| Broche 8 | I/O — Macrocells 1-24 I/O pins |
| Broche 9 | I/O — Macrocells 1-24 I/O pins |
| Broche 10 | GND — Ground (0 V) |
| Broche 11 | I/O — Macrocells 1-24 I/O pins |
| Broche 12 | I/O — Macrocells 1-24 I/O pins |
| Broche 13 | I/O — Macrocells 1-24 I/O pins |
| Broche 14 | I/O — Macrocells 1-24 I/O pins |
| Broche 15 | I/O — Macrocells 1-24 I/O pins |
| Broche 16 | I/O — Macrocells 1-24 I/O pins |
| Broche 17 | I/O — Macrocells 1-24 I/O pins |
| Broche 18 | I/O — Macrocells 1-24 I/O pins |
| Broche 19 | I/O — Macrocells 1-24 I/O pins |
| Broche 20 | I/O — Macrocells 1-24 I/O pins |
| Broche 21 | IN — Dedicated input (1 of 12) |
| Broche 22 | IN — Dedicated input (1 of 12) |
| Broche 23 | IN — Dedicated input (1 of 12) |
| Broche 24 | IN — Dedicated input (1 of 12) |
| Broche 25 | IN — Dedicated input (1 of 12) |
| Broche 26 | IN — Dedicated input (1 of 12) |
| Broche 27 | IN — Dedicated input (1 of 12) |
| Broche 28 | IN — Dedicated input (1 of 12) |
| Broche 29 | IN — Dedicated input (1 of 12) |
| Broche 30 | GND — Ground (0 V) |
| Broche 31 | IN — Dedicated input (1 of 12) |
| Broche 32 | IN — Dedicated input (1 of 12) |
| Broche 33 | I/O — Macrocells 1-24 I/O pins |
| Broche 34 | I/O — Macrocells 1-24 I/O pins |
| Broche 35 | I/O — Macrocells 1-24 I/O pins |
| Broche 36 | I/O — Macrocells 1-24 I/O pins |
| Broche 37 | I/O — Macrocells 1-24 I/O pins |
| Broche 38 | I/O — Macrocells 1-24 I/O pins |
| Broche 39 | I/O — Macrocells 1-24 I/O pins |
| Broche 40 | VCC — +5 V supply |
Applications typiques
EP910PC-35 convient pour 7 applications: Address Decoding & Bus Interface Logic, Legacy Telecom Backplane Glue Logic, Industrial PLC I/O Expansion Logic, Glue Logic Replacement for Multiple 22V10 PALs, Legacy Test & Measurement Instrumentation, Avionics & Military Legacy Systems, 5V Embedded System Glue Logic.
Address Decoding & Bus Interface Logic
The EP910PC-35's 24 macrocells and 240 product terms are well-matched to multi-chip address decoding and bus interface tasks in 5V 80C186/68k/MIPS legacy systems. Its 35 ns propagation delay sits comfortably below typical 8 MHz microprocessor memory-access windows, ensuring glitch-free chip-select generation. The PAL-type architecture and 12 dedicated inputs let designers map full address AND control-signal combinations into a single device, replacing multiple 22V10 or 16L8 PALs and reducing board area. Power consumption is moderate (CMOS static ~100 mW typical), allowing dense logic integration without thermal concerns.
Recommandé
Legacy Telecom Backplane Glue Logic
The EP910PC-35 is widely deployed as glue logic in legacy telecom backplanes (T1/E1 line cards, central-office multiplexers, and digital cross-connects) where 5V PLDs replaced discrete TTL. Its 24 I/O pins and 36 total inputs handle HDLC framing, time-slot switching, and alarm-status encoding. The 35 ns delay is sufficient for sub-30 MHz backplane clocks, and the 40-pin PDIP package simplifies field-replacement on through-hole backplane assemblies. Long-term reliability and 25-year product lifecycle support make it a stable choice for telecom-grade legacy systems.
Recommandé
Industrial PLC I/O Expansion Logic
Industrial PLCs and process controllers from the 1990s-2000s used EPLDs like the EP910PC-35 to expand discrete I/O, debounce mechanical switch inputs, and generate PWM/Stepper control waveforms. The 24 macrocells handle up to 24 isolated output channels or input-filter chains in a single chip, while 12 dedicated inputs feed interrupt, fault, and handshake signals. The 5V supply matches legacy PLC backplanes, and the 40-pin PDIP survives high-vibration environments better than surface-mount equivalents.
Recommandé
Glue Logic Replacement for Multiple 22V10 PALs
A single EP910PC-35 typically replaces 2-3 standard 22V10 PALs in mid-density glue logic designs, cutting board area, power consumption, and BOM cost. The 240 product terms and 24 macrocells handle wide combinational and registered logic functions that would otherwise require cascading PALs with propagation-delay accumulation. With 35 ns pin-to-pin delay, the EP910PC-35 matches 22V10-15 timing while offering 50% more I/O and macrocell resources, making it an efficient consolidation choice for legacy upgrades.
Recommandé
Legacy Test & Measurement Instrumentation
Bench-top oscilloscopes, logic analyzers, and GPIB instruments from the 1990s relied on EP910-class EPLDs for front-panel state machines, GPIB handshake logic, and timing generators. The 24 macrocells support 24-bit binary counters, frequency dividers, and trigger sequencers; the 35 ns delay meets sub-30 MHz clock-domain requirements. The plastic DIP package simplifies bench prototyping and field repair of legacy test equipment still in service at calibration labs and aerospace test stations.
Recommandé
Avionics & Military Legacy Systems
The EP910PC-35 / 883B military-screened variant (EP910DM-40, EP910DM/883B) supports avionics and military legacy platforms where 5V CMOS PLDs with established reliability histories are required. With 24 macrocells and MIL-STD-883B screening, the EP910 family was qualified for radar systems, flight-control computers, and military communications. The 40-pin PDIP with its through-hole leads withstands vibration and thermal cycling better than surface-mount equivalents, and the long-term Altera/Intel PSG support commitment keeps these parts available for sustainment programs.
Recommandé
5V Embedded System Glue Logic
Modern 5V-tolerant embedded controllers and SoCs still benefit from external EPLD glue logic for chip-select generation, interrupt prioritization, and timing-stretch logic. The EP910PC-35's 36 inputs and 24 I/O pins accommodate multiple peripherals sharing a single bus, while its 35 ns delay fits 80 MHz / 50 MHz bus clocks with margin. Designers transitioning from older PAL designs find the EP910 family's MAX+PLUS toolchain familiar, and the 40-pin PDIP eases hand-soldering during prototyping and rework.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP910PC-35 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP910PC-30 | EP910PC-25 | EP910DC-35 | EP910IPC-35 | EP910PC-40 | EP610PC-25 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PDIP-40 | PDIP-40 (same) | PDIP-40 (same) | CerDIP-40 (same DIP outline) | PDIP-40 (same) | PDIP-40 (same) | PDIP-24 (smaller) |
| Propagation Delay | 35 ns | 30 ns (faster) | 25 ns (faster) | 35 ns (same) | 35 ns (same) | 40 ns (slower) | 25 ns (faster) |
| Macrocells | 24 | 24 (same) | 24 (same) | 24 (same) | 24 (same) | 24 (same) | 16 (smaller) |
| I/O Pins | 24 | 24 (same) | 24 (same) | 24 (same) | 24 (same) | 24 (same) | 16 (smaller) |
| Product Terms | 240 | 240 (same) | 240 (same) | 240 (same) | 240 (same) | 240 (same) | 160 (smaller) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Programming | OTP (plastic) | OTP (plastic) | OTP (plastic) | UV-erasable (CerDIP) | OTP (plastic) | OTP (plastic) | OTP (plastic) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principaux différenciateurs
- More I/O pins than 22V10 / 16L8 PALs (24 I/O vs 10/8) for higher-density glue logic consolidation (vs PALCE22V10-15)
- Faster 35 ns speed grade at lower cost than ceramic EP910DC-35 for production runs (vs EP910DC-35 (CerDIP, windowed))
- PAL-type architecture with buried macrocell registers vs simple AND/OR PAL combinational logic (vs PALCE16V8)
Notes de conception
Place a 0.1 uF ceramic decoupling capacitor as close as possible to each VCC pin (pin 40) and a 10 uF tantalum bulk capacitor on the same 5V rail. The EP910PC-35 is a CMOS device with low static current (~5-15 mA typical) but can draw 50-100 mA during high-frequency switching of all 24 macrocells. Estimate: ICC_typ * VCC = 5 V * 10 mA = 50 mW quiescent; add ~30-50 mA switching on top. Adequate decoupling prevents VCC bounce that can corrupt macrocell state.
For 40-pin PDIP layouts, use standard 2.54 mm (100 mil) pin pitch with 1.6 mm (62 mil) drill holes. Keep high-current switching traces away from the EP910PC-35 to avoid ground-bounce coupling into the dedicated inputs. Route clock signals to the dedicated input pins (IN1-IN12) rather than I/O pins when possible, because dedicated inputs route directly to the AND array with predictable delay. If using buried macrocell flip-flops, add a global clock distribution trace with matched length to all synchronous flip-flops.
Three common pitfalls when using the EP910PC-35: (1) Modern Quartus Prime software does NOT support the Classic EPLD family — you must use legacy A+PLUS or MAX+PLUS II, and the original hardware programmer (Altera PLGAS-PLUS or equivalent JEDEC programmer); (2) The plastic DIP package is OTP — once programmed, it cannot be UV-erased; use EP910DC-35 (CerDIP, windowed) during development to avoid wasted parts; (3) The 35 ns delay applies to combinational paths; registered paths add one flip-flop setup time (~5-10 ns) — verify timing at system level, not just the AND/OR path.
The EP910PC-35 in PDIP-40 has a thermal resistance theta_JA of approximately 50-60 C/W (estimated; typical for plastic DIP packages). Estimated: with 50 mA switching current at 5 V (250 mW) and 25 C ambient, junction temperature rises 12-15 C, well within the 0-70 C commercial range. For industrial (-40 to +85 C) applications, switch to EP910IPC-35 (industrial temp grade). No external heatsink is required for any EP910 family variant in PDIP due to low CMOS power dissipation.
Informations de conformité
EP910 family predates RoHS directive (2006); plastic DIP variants were typically manufactured with tin-lead finish. RoHS/REACH status unknown as of 2026-09-10 due to obsolete status and fragmented distributor records. For RoHS-compliant legacy replacements, contact specialty distributors offering lead-free re-plating services. MIL-STD-883B screened variants (EP910DM/883B) are available for aerospace/defense applications.
