Circuits intégrés

27C512-25-X

27C512-25-X - 512Kbit 64Kx8 UV EPROM 250ns | Fujitsu

The Fujitsu 27C512-25-X is a 512 Kbit (65,536 x 8-bit) CMOS ultraviolet-erasable programmable read-only memory (UV EPROM) with a 250 ns access time, housed in a 28-pin package with the JEDEC-approved 27C512 pinout. It operates from a single +5 V power supply with a standard +/-10% tolerance, making it a classic drop-in firmware and code-storage device for legacy embedded systems. An EPROM (Erasable Programmable Read-Only Memory) is a non-volatile memory technology that retains programmed data without power and can be erased in bulk by exposure to ultraviolet light through a quartz window (in the UV variant) before reprogramming. Within the memory hierarchy, EPROMs sit between mask ROM and modern Flash memory, and the 27C512 became one of the most widely standardized 512 Kbit devices across the industry, with JEDEC pinout compatibility across manufacturers. Key features include the 64K x 8 organization, 250 ns access speed grade (sufficient for mid-speed 8-bit and 16-bit microprocessor systems without wait states at moderate clock rates), CMOS technology for low standby power consumption (on the order of tens of microamperes typical in standby, per 27C512 family datasheets), and a single +5 V read-mode supply. Programming is performed at elevated voltage using standard EPROM programming algorithms. Technically, the device uses CMOS memory cells arrayed as 65,536 bytes, address decoding across 15 address lines (A0-A14), and active-low chip enable (/CE) and output enable (/OE) controls supporting standby and read modes. Typical applications include firmware storage in legacy industrial controllers, automotive ECUs, arcade and retro-computing boards, telecom line cards, and test equipment where original EPROMs must be maintained or replaced. Design consideration: verify whether your board requires the UV-erase windowed package or an OTP variant, and confirm the access-time grade meets your microprocessor timing margin at temperature extremes. This page synthesizes distributor sourcing data, drop-in cross-references, and practical design notes for this discontinued Fujitsu memory not found on any single manufacturer datasheet.

USD $2,95 En stock

27C512A-12I/SO

27C512A-12I/SO - 512Kbit CMOS EPROM 120ns | Microchip Technology

The Microchip Technology 27C512A-12I/SO is a 512 Kbit (64K x 8) CMOS One-Time Programmable (OTP) EPROM with a maximum access time of 120 ns, a single 5V supply (4.5V to 5.5V), and a 28-lead SOIC (SO) surface-mount package rated for industrial temperatures from -40C to +85C. An EPROM (Erasable Programmable Read-Only Memory) is a non-volatile memory IC whose contents are programmed once at the factory or in the lab via a dedicated programming voltage, retaining firmware permanently without power. Within the memory hierarchy, EPROM sits alongside OTP ROM and precedes flash memory as a code-storage device; it belongs to the broader category of semiconductor memory ICs and is commonly used to hold boot code, lookup tables, and fixed firmware in embedded systems. Key features include high-speed CMOS technology for low power consumption, 25 mA typical active current, and just 30 uA standby current, which keeps system power budgets low. Outputs are 3-state with common I/O, allowing direct bus connection and easy memory expansion. The device operates fully asynchronously, requiring no clock, and features Auto ID to aid automated programming. Factory programming service is also available from Microchip. Technically, the 27C512A family uses a CMOS process that substantially reduces static power compared with NMOS EPROMs of the 27512 era. The 64K x 8 organization provides 65,536 addressable bytes, addressed through 15 address lines (A0-A14) with 8 bidirectional data lines (DQ0-DQ7). Chip enable (/E) and output enable (/OE) controls give designers flexible bus interface and fast access timing, with a worst-case address-to-output delay of 120 ns for the -12 speed grade. Typical applications include firmware storage for legacy embedded controllers, industrial automation equipment, automotive ECUs operating in the industrial temperature band, telecommunications line cards, and repair or maintenance spares for long-life systems still using 5V EPROM-based designs. Its 5V logic compatibility makes it a natural fit for older bus architectures. Design consideration: as a one-time-programmable device, the 27C512A cannot be erased and reprogrammed, so verify code thoroughly or pre-qualify with a UV-erasable windowed package before committing to OTP production units. Ensure /OE is not tied low during chip-enable transitions to avoid bus contention. This page synthesizes distributor availability, drop-in same-family alternatives, pinout data, and practical design notes not found in the manufacturer datasheet, providing a single engineering reference for sourcing and designing with this legacy memory IC.

USD $2,85 En stock

27C512L-15T

27C512L-15T - 512Kbit 64Kx8 CMOS EPROM 150ns | WSI

The WaferScale Integration (WSI) 27C512L-15T is a 512 Kilobit (64K x 8-bit) low-power CMOS UV/OTP EPROM memory with a 150 ns access time, single +5 V power supply operation, and a JEDEC-approved pinout supplied in a 32-pin PLCC package (T suffix). The low-power (L) grade reduces active and standby current consumption, with approximately 20 uA typical CMOS standby current per the 27C512 family datasheet. An EPROM (Erasable Programmable Read-Only Memory) is a non-volatile memory IC whose contents are programmed electrically and erased with UV light in windowed packages (OTP versions are not erasable). Within the memory hierarchy, the 27C512 belongs to the classic parallel EPROM family descended from the Intel 2716/2764/27128/27256 lineage, occupying the 512 Kbit density point with a 64K x 8 organization that made it a de facto standard firmware storage device in embedded systems. Key features include fast access time options as low as 45 ns across the family (150 ns for the -15 speed grade), a single +5 V power supply with a standard +/-10% tolerance, a +12.5 V VPP programming voltage with 100% Flashrite programming, and a JEDEC-approved pinout that guarantees mechanical and electrical interchangeability across manufacturers such as TI (TMS27C512), STMicroelectronics, Intel, and Philips. The CMOS process delivers low power consumption during both active read and standby operation, making the L-grade variant well suited to battery-backed and power-sensitive designs. Address inputs A0-A15, eight tri-state data outputs O0-O7, chip enable (CE), output enable (OE), and VPP control provide a straightforward parallel memory interface to 8-bit microcontrollers and processors. Typical applications include legacy firmware storage in industrial control systems, automotive ECUs, telecom line cards, arcade and test equipment, and embedded BIOS/firmware replacement in board-level maintenance and repair. Design consideration: for new designs, prefer flash-based replacements (SST39SF512 or similar) that are pin-compatible; for repair and maintenance of existing sockets, the 27C512L-15T drop-in family preserves the original footprint and timing budget. This page synthesizes distributor availability data, cross-reference options, and practical engineering guidance not consolidated in any single manufacturer datasheet.

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2VM3104

2VM3104 - Versal Prime Gen 2 Adaptive SoC | AMD | 23x23mm

The AMD 2VM3104 is a Versal Prime Series Gen 2 adaptive SoC designed for space-constrained embedded applications such as Pro AV, broadcast, and industrial IoT. It integrates a quad-core Arm Cortex-A78AE application processing unit (APU) with programmable logic, delivering up to 100K DMIPS of scalar compute in a compact 23 x 23 mm package. This device is part of AMD's second-generation Versal Prime family, which offers up to 10x scalar compute performance compared to previous adaptive SoCs. An adaptive SoC (System-on-Chip) combines a processor subsystem (PS) with programmable logic (PL) on a single device, enabling hardware acceleration and flexible I/O. The Versal Prime Series Gen 2 targets embedded systems requiring high compute density and low latency, bridging the gap between traditional FPGAs and application-specific standard products (ASSPs). The 2VM3104 is positioned as an entry point for customers evaluating the Versal Prime Gen 2 family, with availability expected in 2027. Key features of the 2VM3104 include a quad-core Arm Cortex-A78AE APU with 64 KB L1 cache, a 23 x 23 mm package that is 27% smaller than previous second-generation Versal Prime devices, and higher programmable logic density per square millimeter compared to similarly sized 8-core devices. The device supports up to 100K DMIPS of scalar compute, making it suitable for real-time control and signal processing. Technically, the 2VM3104 leverages AMD's advanced process technology to achieve a balance of power efficiency and performance. The programmable logic fabric allows custom accelerators, while the APU handles general-purpose computing. The compact package enables designs with reduced board area, critical for space-constrained systems. Typical applications include Pro AV equipment (video processing, audio mixing), broadcast infrastructure (encoding, transcoding), and industrial IoT gateways (edge computing, machine vision). The device's small footprint and high compute density make it ideal for these markets. When designing with the 2VM3104, consider thermal management due to the high compute density in a small package. Adequate cooling and power delivery are essential to maintain performance and reliability.

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2VM3254

2VM3254 - Versal Prime Gen 2 Adaptive SoC | AMD

The AMD 2VM3254 is a Versal Prime Series Gen 2 adaptive SoC designed for space-constrained embedded applications. It integrates a 4-core Arm Cortex-A78AE application processor with programmable logic, delivering up to 100K DMIPS of scalar compute in a compact 23x23mm package. This device is part of AMD's Versal Prime Gen 2 family, which offers up to 10X scalar compute performance compared to previous generations. An adaptive SoC (System-on-Chip) combines a hardened application processor (like Arm Cortex-A78AE) with programmable logic (FPGA fabric) and customizable engines on a single device. This architecture allows designers to implement both software-defined and hardware-accelerated functions, bridging the gap between traditional microprocessors and FPGAs. The Versal Prime Series Gen 2 targets embedded systems requiring high compute density, low latency, and flexible I/O. Key features of the 2VM3254 include a 23x23mm package (27% smaller than the previous minimum), 4-core Cortex-A78AE processor, and support for Pro AV, broadcast, and industrial IoT applications. The device provides high programmable logic density per square millimeter, enabling complex designs in compact form factors. It also supports the Versal Prime Gen 2 ecosystem, including design tools and early access programs. Technically, the 2VM3254 leverages AMD's adaptive compute acceleration platform (ACAP) architecture, combining scalar engines (Arm cores), adaptable engines (programmable logic), and intelligent engines (AI cores) with a network-on-chip (NoC) interconnect. This heterogeneous architecture allows concurrent execution of software and hardware tasks, optimizing performance per watt for edge applications. Typical applications include Pro AV video processing, broadcast infrastructure, industrial IoT gateways, and edge AI systems. The compact package makes it ideal for space-constrained designs where board area is critical. The device also serves as an entry point for customers evaluating Versal Prime Gen 2 before migrating to larger devices like the 2VM3654. When designing with the 2VM3254, consider the power delivery network (PDN) requirements for the multi-rail SoC, including core, I/O, and memory voltages. Use AMD's power estimation tools and reference designs to optimize decoupling and thermal management in the 23x23mm package.

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2VM3358

2VM3358 - Versal Prime Gen 2 Adaptive SoC | AMD

The AMD 2VM3358 is a Versal Prime Series Gen 2 adaptive SoC, featuring 8 Arm Cortex-A78AE application cores and 10 Cortex-R52 real-time cores. This device delivers up to 10x scalar compute compared to previous AMD Versal or Zynq UltraScale+ adaptive SoCs, making it a high-performance heterogeneous computing platform for demanding embedded applications. The 2VM3358 is part of the earliest Versal Prime Gen 2 devices, alongside the 2VM3858 and 2VM3558, and is available in the SFVA1089 package. An adaptive SoC (System-on-Chip) is a heterogeneous computing device that combines programmable logic (FPGA fabric) with hardened processing subsystems, including application processors, real-time processors, and various I/O interfaces. In the Versal architecture, the scalar engines (Cortex-A78AE and Cortex-R52) handle general-purpose and real-time processing, while the programmable logic provides custom hardware acceleration. This hierarchy enables a single device to replace multiple discrete components, reducing system complexity and power consumption. Key features of the 2VM3358 include 8 Arm Cortex-A78AE application cores for high-performance Linux or RTOS applications, 10 Cortex-R52 real-time cores for deterministic, low-latency control tasks, and the Versal adaptive architecture that allows hardware acceleration to be tailored to specific workloads. The device supports up to 10x scalar compute performance versus prior generations, enabling advanced AI, signal processing, and control applications in a single chip. Technically, the 2VM3358 leverages AMD's advanced process technology and the Versal platform's integrated design tools, including Vitis and Vivado. The device's heterogeneous architecture allows developers to partition workloads between scalar processing, programmable logic, and dedicated AI engines (if present in the specific variant). The SFVA1089 package provides a high-density interconnect, supporting high-speed transceivers and memory interfaces for system-level integration. Typical applications for the 2VM3358 include avionics, factory automation, building automation, grid infrastructure, and other industrial or aerospace systems requiring high compute density and real-time responsiveness. The device's combination of scalar performance and programmable logic makes it suitable for edge computing, machine vision, and motor control applications. When designing with the 2VM3358, consider the power consumption of the smallest system configuration, as documented in AMD's support forums. Proper thermal management and power supply design are critical due to the device's high performance and integration level. The SFVA1089 package requires careful PCB layout to manage signal integrity and power distribution.

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2VM3454

2VM3454 - Versal Prime Gen 2 Adaptive SoC | AMD

The AMD 2VM3454 is a Versal Prime Series Gen 2 adaptive SoC designed for space-constrained embedded applications such as Pro AV, broadcast, and industrial IoT. It integrates a quad-core Arm Cortex-A78AE application processor, six real-time Arm Cortex-R52 cores, and a Mali-G78AE GPU, delivering up to 100K DMIPS of scalar compute in a compact 23 x 23 mm package. This device is part of AMD's second-generation Versal Prime family, which offers up to 10x scalar compute performance compared to existing adaptive SoCs. An adaptive SoC (System-on-Chip) combines programmable logic (FPGA fabric) with a hardened processor subsystem (PS) and other dedicated engines on a single device. This architecture allows designers to implement custom hardware accelerators in the programmable logic while running complex software on the application cores, bridging the gap between traditional FPGAs and application processors. The Versal Prime Series Gen 2 targets embedded systems requiring high compute density, low latency, and flexible I/O. Key features of the 2VM3454 include the quad-core Cortex-A78AE with 64 KB L1 cache, six Cortex-R52 real-time cores, and a Mali-G78AE GPU. The device is available in a 23 x 23 mm package, enabling compact PCB designs. It supports up to 100K DMIPS of scalar compute, making it suitable for real-time processing and AI inference at the edge. The Versal architecture provides a unified design environment with AMD Vivado and Vitis tools. Technically, the 2VM3454 leverages AMD's advanced 7nm-class process technology, offering a balance of performance and power efficiency. The programmable logic fabric supports high-speed transceivers and flexible I/O standards, while the processor subsystem handles complex control and data processing tasks. The device includes integrated security features and supports functional safety for industrial and automotive applications. Typical applications include Pro AV video processing, broadcast infrastructure, industrial IoT gateways, and edge AI systems. The compact package and high compute density make it ideal for space-constrained designs where performance and power efficiency are critical. When designing with the 2VM3454, consider the power delivery network and thermal management. The device requires multiple voltage rails and adequate decoupling. Use the AMD power estimator tool to calculate power consumption and design the thermal solution accordingly.

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2VM3558

2VM3558 - Versal Prime Gen2 Adaptive SoC | AMD

The AMD 2VM3558 is a Versal Prime Series Gen 2 Adaptive SoC, part of the second-generation Versal family that integrates Arm Cortex-A78AE application processors, Cortex-R52 real-time processors, and programmable logic in a single device. It is designed for high-performance embedded applications requiring up to 10x scalar compute compared to previous Versal or Zynq UltraScale+ devices. The 2VM3558 is available in the SSVA1440 package, offering a balance of logic density, I/O, and transceiver capabilities for mid-range designs. An Adaptive SoC is a heterogeneous computing platform that combines scalar processing (Arm cores), adaptable hardware (FPGA fabric), and intelligent engines (DSP, AI) on a single chip. This architecture allows hardware acceleration to be customized post-manufacturing, enabling performance and efficiency gains over fixed-function SoCs. The Versal Prime Gen2 series targets embedded systems where flexibility, performance, and long-term adaptability are critical. Key features of the 2VM3558 include 8 Arm Cortex-A78AE application cores and 10 Cortex-R52 real-time cores, delivering up to 10x scalar compute versus prior generations. It supports PCIe Gen5, 4GB LPDDR5x memory, and GTYP transceivers up to 32Gbps, making it suitable for high-bandwidth data movement. The device also includes a Video Codec Unit and Image Signal Processor, enabling advanced media processing. With up to 1188K logic cells and 543K LUTs, it provides substantial programmable logic resources. Technically, the 2VM3558 leverages AMD's 7nm process technology and advanced packaging to integrate multiple dies, including the programmable logic, processing system, and transceivers. The SSVA1440 package offers a high pin count for extensive I/O and memory interfaces. The device supports industrial temperature ranges (-40°C to +85°C) and is designed for reliability in harsh environments. Typical applications include avionics, defense, industrial automation, and edge computing, where the combination of high-performance scalar processing and adaptable hardware is essential. The 2VM3558 is also used in system-on-modules (SoMs) for rapid prototyping and deployment. When designing with the 2VM3558, consider power delivery complexity: the device requires multiple voltage rails (e.g., 0.85V core, 1.8V I/O) and careful sequencing. Use AMD's power management reference designs and ensure adequate decoupling for high-speed transceivers.

USD $900,00 En stock

54FCT162245CTEB

54FCT162245CTEB - 16-Bit Bidirectional Transceiver, 5.5V, 48-CerPack | Renesas

The Renesas 54FCT162245CTEB is a 16-bit, high-speed, low-power bidirectional transceiver built on advanced dual-metal CMOS technology and housed in a 48-pin CERPACK (CERDIP-style sidebraze) ceramic package. It functions as either two independent 8-bit transceivers or one 16-bit transceiver, providing synchronous communication between two buses with 3-state outputs and a typical propagation delay of 4.5 ns at 50 pF load. The device operates across a 4.5 V to 5.5 V VCC range, with a wide -55 C to +125 C operating temperature window suited for military and aerospace programs. A bidirectional transceiver is a bus-interface IC that drives signals in either direction between two ports under the control of direction-control inputs, while 3-state outputs allow multiple devices to share a bus by entering a high-impedance state when disabled. The 54FCT162245CTEB belongs to the FCT (Fast CMOS Technology) logic family, positioned in the taxonomy as transceiver -> bus interface IC -> logic IC -> integrated circuit. It is engineered as a low-power CMOS replacement for legacy ABT (Advanced BiCMOS Technology) functions, delivering balanced drive strength (16 mA source/sink) with typical output skew below 250 ps for synchronous timing budgets. Key features include 16 mA balanced output drive on both ports, 500 uA typical quiescent supply current, Schmitt-trigger inputs for slow-edged or noisy signals, and an output-enable pin for each 8-bit half. ESD protection exceeds 2000 V per MIL-STD-883, Method 3015, and 200 V using the machine model. The device's 0.5 micron CMOS process yields the speed of bipolar ABT logic with a fraction of the power dissipation, simplifying thermal management in dense backplane designs. Architecturally, the transceiver uses dual-metal CMOS to achieve sub-5 ns propagation while keeping ICC low enough for portable instrumentation. Each 8-bit half is controlled independently: a DIR pin sets direction and an OE pin enables the outputs, so a single device can bridge two buses of different widths on the same PCB. Typical tSK(o) below 250 ps makes the part usable in clock-distribution and registered-buffer applications where edge alignment matters. Typical applications include military and aerospace backplanes, point-to-point board-to-board data buffering, 16-bit or 8-bit memory/address bus isolation, and synchronous inter-board communication in VME, cPCI, or custom parallel data links. The wide operating temperature range and ceramic hermetic package also suit downhole, avionics, and radiation-tolerant programs where plastic packages are not acceptable. When designing with this device, treat the CERPACK footprint as non-substitutable with plastic SOIC/DIP variants - any drop-in replacement must share the same 48-pin CERPACK land pattern. For new designs targeting commercial temperature ranges, consider the equivalent 74FCT162245T plastic-package family, but verify pinout compatibility before substitution. This page synthesizes distributor pricing, drop-in equivalents, and CERPACK-specific design notes that are not consolidated in the manufacturer datasheet alone.

USD $4,75 En stock

553SCMGI8

553SCMGI8 - Low Skew 1:4 LVCMOS Clock Buffer 200 MHz | Renesas

The Renesas 553SCMGI8 is a low skew, single-input to four-output LVCMOS clock buffer packaged in an 8-pin UFDFN (2x2 mm) with exposed pad. The device accepts one LVCMOS input and distributes four LVCMOS outputs with best-in-class additive phase jitter of sub-50 fs RMS and an extremely low output-to-output skew of 50 ps. It supports three common supply rails - 1.8 V, 2.5 V, and 3.3 V - through a wide VDD range of 1.71 V to 3.465 V, making it ideal for multi-voltage system designs. A clock buffer (also called clock fanout buffer or clock driver) is a timing IC that takes a single reference clock and replicates it onto multiple outputs while preserving edge fidelity and minimizing additive jitter. Clock buffers sit in the timing tree hierarchy between a PLL/oscillator and downstream clock-consuming devices (CPUs, FPGAs, ASICs, SerDes, memory controllers). By regenerating clean edges with low skew, they ensure deterministic timing across complex boards. Buffers are simpler than PLLs but must add negligible jitter so they do not degrade system-level phase noise budgets. The 553SCMGI8's headline specifications include <50 fs RMS additive jitter (12 kHz to 20 MHz), 50 ps output skew, 200 MHz maximum operating frequency, and -40 C to +105 C industrial operating range. The 8-pin UFDFN occupies only 2x2 mm of PCB area, enabling dense layouts in space-constrained designs. The exposed pad (EP) provides a low thermal resistance path, allowing continuous operation at high frequencies without derating. Architecturally, the 553S uses a low-jitter differential-pair input stage followed by matched output drivers and a precision skew-tuning network. All four outputs are designed with matched propagation delay, which is the foundation of the 50 ps skew specification. The device integrates LVCMOS input hysteresis, output slew-rate control, and internal bias generation - no external components are required beyond a single 0.01 uF decoupling capacitor on VDD. Typical applications include networking line cards, telecom baseband cards, server motherboards, FPGA/ASIC clock fanout, and storage area network controllers. The 200 MHz ceiling comfortably covers Ethernet, PCI Express Gen1/2 reference clocks, and most general-purpose processor clocking. When designing with this part, place a 0.01 uF decoupling capacitor as close as possible to VDD (pin 1) and GND (pin 4 / EP), and use a 33 ohm series termination resistor on each output if the trace exceeds 1 inch. Match output trace lengths to within 50 ps of equivalent electrical length to fully exploit the device's skew budget. This page synthesizes distributor pricing, application guidance, and drop-in alternatives that complement the Renesas datasheet with practical sourcing information.

USD $0,96 En stock

553SDCGI

553SDCGI - 1:4 LVCMOS Clock Buffer 200MHz 8-SOIC | Renesas

The Renesas 553SDCGI is a low-skew, single-input to four-output LVCMOS clock buffer IC that delivers best-in-class additive phase jitter of sub 50 femtoseconds and supports clock frequencies up to 200 MHz, housed in an 8-pin SOIC (3.90 mm) package. Designed for high-performance clock distribution, the device operates from a 2.375 V to 3.465 V supply and is well-suited to networking, telecom, and compute platforms requiring tight timing margins. A clock buffer (also called a clock fanout buffer or clock distribution IC) is a type of timing IC that replicates one input clock signal across multiple outputs with minimal added jitter and controlled skew. Within the broader timing hierarchy, clock buffers sit between clock generators (oscillators, PLLs, crystal units) and clock-consuming loads (processors, FPGAs, ASICs, serializers). The 553S family targets applications where PCB trace lengths, fanout requirements, or isolation needs make direct point-to-point clock distribution impractical. Key features of the 553SDCGI include sub-50 fs additive phase jitter (12 kHz to 20 MHz integration band), 1:4 fanout with matched output-to-output skew, LVCMOS-compatible outputs, and a low additive jitter profile that preserves source-clock integrity. The device also integrates an output enable function for power-saving modes and supports industrial temperature operation. Compared with multi-PLL clock trees, the 553S delivers cleaner, more deterministic signal distribution. The 553S architecture uses a low-jitter input receiver followed by a matched-output driver tree, ensuring that all four outputs remain tightly aligned in both frequency and phase. This topology makes the part especially attractive for distributing reference clocks to multiple ADCs, DACs, FPGA transceivers, or SERDES channels where inter-channel timing mismatch would degrade system performance. Typical applications include Ethernet switches and routers, telecom base stations, PCIe and SAS reference-clock fanout, FPGA/ASIC clock distribution, test and measurement instrumentation, and storage area networks. The 50 fs additive jitter specification is particularly valuable for high-speed serial links where the recovered clock's eye margin is sensitive to phase noise. When designing with the 553SDCGI, place a 0.01 uF decoupling capacitor directly between VDD (pin 1) and GND (pin 4) to minimize supply-induced jitter. Use 33 ohm series-termination resistors on outputs when the trace length exceeds 1 inch to control reflections and preserve signal integrity at 200 MHz edges. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing a single reference for engineers evaluating the 553SDCGI for new designs or replacement of legacy clock distribution circuits.

USD $2,55 En stock

5962-0423001QXC

5962-0423001QXC - 14-Bit 80 MSPS Military ADC QML Q | Analog Devices

The Analog Devices 5962-0423001QXC is a high-speed, high-performance monolithic 14-bit analog-to-digital converter (ADC), also known as the AD6645ASQ/QMLQ, housed in a 52-lead thermally-enhanced hermetic ceramic QFP package. The device is 100% production tested at 70 MHz analog input and 150 MHz at -35C to +85C case temperature, providing guaranteed dynamic performance across military temperature ranges. The SMD part number 5962-0423001QXC indicates QML Q qualification per MIL-PRF-38535, making it suitable for high-reliability defense and aerospace applications. What is an ADC? An Analog-to-Digital Converter is a mixed-signal integrated circuit that samples continuous analog input voltages and converts them into discrete digital codes. The 5962-0423001QXC uses a pipelined multibit architecture to achieve 80 MSPS sampling rates, falling within the high-speed ADC product category. Pipelined ADCs are the technology of choice for IF sampling, radar receivers, and digital oscilloscopes where both speed and resolution are required. Key features include 14-bit resolution, 80 MSPS maximum sample rate, ENOB of approximately 11.5 bits at Nyquist input, and SFDR exceeding 80 dBc. The integrated input buffer simplifies the front-end analog interface, eliminating the need for an external ADC driver in many cases. The device operates from a single 3.3V analog supply and 3.3V digital supply with separate grounds for noise isolation. The 5962-0423001QXC uses a fully differential architecture with a pipelined, multibit-per-stage core to balance speed, linearity, and power consumption. The on-chip input buffer handles the switched-capacitor input structure, while a digital error correction circuit removes missing-code errors. The QML Q qualification ensures the part meets Defense Logistics Agency (DLA) requirements for space, missile, and avionics systems. Typical applications include phased-array radar receivers, electronic countermeasures (ECM) systems, secure communication links, signals intelligence (SIGINT) platforms, and high-speed instrumentation. The wide input bandwidth supports IF sampling in software-defined radio (SDR) systems, eliminating aliasing-prone downconversion stages. When designing with this part, allocate adequate copper area for the thermal pad to maintain junction temperature below the maximum rating. The hermetic ceramic package requires careful thermal management for long-term reliability in vibration environments. Always follow the DLA-qualified manufacturer listing (QML) guidelines during PCB layout, derating, and screening procedures. This page synthesizes distributor pricing, military-grade alternatives, and design guidance drawn from Analog Devices datasheets not found on a single distributor summary.

USD $218,50 En stock

5962-85127023A

5962-85127023A - 12-Bit SAR ADC, 28-LCC | Analog Devices

The 5962-85127023A is a military-grade, 12-bit successive-approximation analog-to-digital converter (ADC) manufactured by Analog Devices Inc. It is the SMD (Standard Microcircuit Drawing) version of the AD574A, a complete 12-bit ADC with 3-state output buffer circuitry for direct interface to an 8- or 16-bit microprocessor bus. The device features a single input channel, a SAR architecture, and is packaged in a 28-lead ceramic leadless chip carrier (28-LCC) measuring 11.43x11.43 mm. It includes an on-chip high-precision voltage reference and clock, guaranteeing full-rated performance without external circuitry or clock signals. An analog-to-digital converter (ADC) is an electronic component that converts continuous analog signals into discrete digital numbers. The SAR (successive-approximation register) architecture is a popular ADC topology that performs a binary search through all possible quantization levels before converging on the final digital output. This ADC belongs to the data acquisition subsystem, which is a critical part of any digital signal processing chain, bridging the analog world to digital processors. The 5962-85127023A is designed for high-reliability applications, particularly in aerospace, defense, and industrial environments where precision and durability are paramount. Key features of the 5962-85127023A include 12-bit resolution, a single-ended input, and a parallel output interface. The device operates from a standard ±12V and +5V power supply, and its internal reference and clock eliminate the need for external components, simplifying design. The 28-LCC package is hermetically sealed, providing excellent protection against moisture and mechanical stress, making it suitable for harsh environments. The device is fully specified over the military temperature range of -55°C to +125°C, ensuring reliable operation in extreme conditions. Technically, the AD574A design uses a precision voltage reference and a successive-approximation register to achieve high accuracy and speed. The 3-state output buffers allow direct connection to a microprocessor bus without additional interface logic, reducing system complexity. The device's conversion time is typically 25 microseconds, providing a throughput of up to 40 kSPS, which is adequate for many industrial and aerospace data acquisition applications. The internal clock ensures consistent conversion timing, and the device can be easily configured for 8-bit or 16-bit bus operation via the 12/8 control pin. Typical applications for the 5962-85127023A include military avionics, radar systems, industrial process control, and test and measurement equipment. Its high reliability and wide temperature range make it ideal for mission-critical systems where failure is not an option. The device's parallel interface simplifies integration with microcontrollers and DSPs, and its internal reference reduces external component count, saving board space and improving system reliability. When designing with this ADC, ensure that the analog input signal is properly buffered and filtered to avoid aliasing and to maintain signal integrity. The power supply should be well-regulated and decoupled with 0.1µF ceramic capacitors close to the device pins. The digital output lines should be terminated appropriately to minimize reflections and noise.

USD $25,00 En stock

5962-8871901MXA

5962-8871901MXA - 12-Bit Quad DAC, 28-CDIP | Analog Devices

The 5962-8871901MXA is a military-grade, 12-bit quad digital-to-analog converter (DAC) from Analog Devices, part of the AD664 family. It integrates four complete voltage-output DACs on a single monolithic IC, housed in a 28-pin ceramic dual-in-line package (CDIP). This device is designed for precision analog output in harsh environments, offering double-buffered input latches and data readback functionality. It operates over the full military temperature range and is compliant with MIL-STD-883, making it suitable for aerospace, defense, and industrial applications. A digital-to-analog converter (DAC) is an electronic component that converts digital binary data into an analog voltage or current. The AD664 is a quad DAC, meaning it contains four independent DAC channels on one chip, each with its own output. This architecture is essential in multi-channel control systems where multiple analog signals must be generated simultaneously, such as in servo control, waveform generation, and automatic test equipment. DACs are a subset of data converters, which also include analog-to-digital converters (ADCs), and are fundamental building blocks in mixed-signal systems. Key features of the 5962-8871901MXA include 12-bit resolution, four DAC channels, and a double-buffered input latch structure that allows simultaneous update of all outputs. The device supports 4-, 8-, or 12-bit parallel word formats, enabling flexible interfacing with a wide range of microprocessors. A reset function clears all registers to a known state, and the data readback feature allows verification of written data. The R-2R ladder architecture ensures monotonicity and low glitch energy. Technically, the AD664 uses a segmented R-2R ladder network for each DAC, providing excellent linearity and low output noise. The double-buffered latches allow the host processor to write to all four DACs independently and then update them simultaneously with a single strobe, which is critical for applications requiring synchronized analog outputs. The device operates from a single +12V supply and provides a bipolar output range of ±10V, with a settling time of typically 10 µs. Typical applications include precision servo control systems, automatic test equipment, and military avionics. The 5962-8871901MXA is also used in industrial process control and instrumentation where multiple analog outputs are needed. Its military-grade qualification ensures reliable operation in extreme temperatures and vibration environments. When designing with this DAC, ensure that the digital supply and analog supply are properly decoupled to minimize noise coupling. The reference input should be driven by a low-impedance source to maintain accuracy. Also, consider the output settling time when designing the update rate of the system.

USD $250,00 En stock

5962-8965501LA

5962-8965501LA - 12-Bit Military ADC | Analog Devices

The 5962-8965501LA is a 12-bit analog-to-digital converter (ADC) manufactured by Analog Devices, designed for military-grade applications. It features 24 terminals, a wide operating temperature range of -55°C to +125°C, and a fast conversion time of 10.4 microseconds. This device is part of the 5962 series, which is known for high reliability and performance in harsh environments. An analog-to-digital converter (ADC) is a critical component in electronic systems that converts continuous analog signals into discrete digital values for processing by microcontrollers, DSPs, or FPGAs. The 5962-8965501LA is a successive approximation register (SAR) type ADC, which offers a good balance of speed, resolution, and power consumption. It is commonly used in data acquisition systems, industrial control, and military avionics where precision and reliability are paramount. Key features of the 5962-8965501LA include 12-bit resolution, which provides 4096 discrete levels, ensuring high accuracy in signal conversion. The device operates from a 5V supply, making it compatible with standard logic levels. Its military temperature range ensures operation in extreme conditions, and the 10.4 µs conversion time allows for sampling rates up to approximately 96 kSPS, suitable for many real-time applications. Technically, the ADC uses a SAR architecture with an internal sample-and-hold circuit, providing excellent linearity and low power dissipation. The device is packaged in a ceramic DIP (CDIP) or similar hermetic package, ensuring protection against moisture and mechanical stress. The 5962-8965501LA is compliant with MIL-STD-883, a military standard for microcircuits, guaranteeing its robustness and long-term reliability. Typical applications include military radar systems, missile guidance, avionics data acquisition, and industrial process control. Its wide temperature range and high reliability make it ideal for aerospace and defense applications where failure is not an option. When designing with this ADC, ensure proper decoupling of the power supply and reference voltage to minimize noise. The conversion start signal should be synchronized with the system clock to avoid timing errors. Additionally, the digital output should be buffered to drive capacitive loads without degradation.

USD $29,00 En stock

5962-9078501MLA

5962-9078501MLA - 12-Bit Dual DAC, MIL-STD-883 | Analog Devices

The 5962-9078501MLA is a military-grade, 12-bit dual digital-to-analog converter (DAC) manufactured by Analog Devices Inc. It is designed for high-reliability applications requiring precision analog output in harsh environments. The device features two independent DAC channels, each providing a 12-bit resolution with a parallel interface. It operates from dual supplies of ±11.4V to ±15.75V and is packaged in a 24-pin ceramic dual-in-line package (CDIP) with a 0.300-inch (7.62mm) body width. The operating temperature range is -55°C to +125°C, making it suitable for aerospace, defense, and industrial applications. A digital-to-analog converter (DAC) is an electronic component that converts digital binary data into an analog voltage or current. It is a fundamental building block in data acquisition systems, where it translates digital signals from microprocessors or DSPs into real-world analog signals for control, measurement, or audio reproduction. DACs are categorized by resolution (number of bits), speed (conversion rate), and interface type (parallel or serial). The 5962-9078501MLA is a parallel-interface, 12-bit dual DAC, meaning it can simultaneously update two analog outputs from a single digital input bus, which is essential for applications like waveform generation, motor control, and calibration systems. Key features of the 5962-9078501MLA include its dual-channel architecture, which saves board space and reduces component count in multi-channel systems. The device is screened to MIL-STD-883, ensuring it meets stringent military reliability standards for temperature, shock, and vibration. The parallel interface allows for fast data transfer, with a typical settling time of [DATA_NEEDED: settling time] microseconds. The analog output voltage range is -5V to +5V, providing a bipolar output swing suitable for bipolar signal generation. The device also features an internal reference, simplifying external component requirements. Technically, the 5962-9078501MLA uses a segmented architecture to achieve 12-bit linearity, with a typical integral nonlinearity (INL) of [DATA_NEEDED: INL] LSB and differential nonlinearity (DNL) of [DATA_NEEDED: DNL] LSB. The device operates from dual supplies, allowing it to generate both positive and negative output voltages. The digital interface is TTL/CMOS compatible, and the device includes a chip select and write control for easy integration with microprocessors. The ceramic package provides excellent thermal and mechanical stability, crucial for military and aerospace environments. Typical applications include precision instrumentation, avionics control systems, radar signal generation, and military communication equipment. The device's wide operating temperature range and MIL-STD-883 screening make it ideal for mission-critical systems where reliability is paramount. In avionics, it can be used to generate analog control signals for flight surfaces, while in radar systems, it can produce precise analog waveforms for signal processing. When designing with this device, ensure that the power supply decoupling is adequate, with 0.1uF ceramic capacitors placed close to the supply pins. The reference input should be bypassed with a 10uF tantalum capacitor to reduce noise. Also, consider the settling time and update rate requirements of your application to ensure the DAC can meet the system's speed demands.

USD $33,52 En stock

5962-9169003M3A

5962-9169003M3A - 12-Bit SAR ADC, 28-LCC | Analog Devices

The 5962-9169003M3A is a military-grade, 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) from Analog Devices, designed for high-reliability applications. It features two input channels, a single SAR architecture, and a parallel interface, packaged in a 28-lead ceramic leadless chip carrier (LCC) measuring 11.43x11.43 mm. This device is part of the AD674B/AD774B family, which are complete 12-bit ADCs with on-chip voltage reference and clock, requiring only power supplies and control signals for operation. An analog-to-digital converter (ADC) is a critical component in electronic systems that converts continuous analog signals into discrete digital values for processing by microcontrollers, DSPs, or FPGAs. The SAR architecture is widely used for medium-to-high resolution conversions at moderate speeds, offering a good balance of speed, power, and cost. This ADC falls under the broader category of data converters, which are essential in applications ranging from industrial automation to aerospace instrumentation. Key features of the 5962-9169003M3A include 12-bit resolution, a maximum conversion time of 15 microseconds, and three-state output buffers for direct interface to 8- and 16-bit microprocessor buses. It is pin-compatible with the industry-standard AD574A but offers faster conversion time and lower power consumption. The device operates over the full military temperature range and is screened to MIL-STD-883, ensuring reliability in harsh environments. Technically, the ADC integrates a high-precision voltage reference and clock, simplifying system design. The parallel output interface allows for high-speed data transfer, and the three-state buffers enable bus sharing. The device requires dual supplies, typically +5V and ±12V or ±15V, and consumes low power compared to earlier AD574A designs. Typical applications include military avionics, industrial process control, medical instrumentation, and test and measurement equipment where precision and reliability are paramount. The wide operating temperature range and MIL-STD-883 screening make it suitable for defense and aerospace systems. When designing with this ADC, ensure proper decoupling of the power supplies and a clean analog ground plane to achieve specified performance. The on-chip reference and clock reduce external component count, but external bypass capacitors are recommended for optimal noise performance.

USD $80,00 En stock

5962-9470301MYA

5962-9470301MYA - 8-Bit 50MSPS Dual Flash ADC | ADI | MIL-STD-883

The Analog Devices 5962-9470301MYA is a radiation-tolerant dual-channel 8-bit flash analog-to-digital converter sampling at 50 MSPS per channel, housed in a 44-pin JLCC (J-Lead Ceramic Chip Carrier, 16.39x16.39 mm) hermetic package qualified to MIL-STD-883. It is the SMD (Standard Microcircuit Drawing) variant of the legacy AD9058 dual ADC and operates from a single +5 V supply with CMOS-compatible parallel outputs. A flash ADC (also called a direct-conversion ADC) is a type of analog-to-digital converter that uses a parallel bank of 2^N - 1 comparators against a resistor-ladder reference to digitize an analog input in a single clock cycle. Within the broader data-converter hierarchy, this places it as: flash ADC -> high-speed ADC -> analog-to-digital converter -> data converter -> mixed-signal IC. Flash architecture is the fastest ADC topology but is power-hungry and area-intensive, limiting practical resolution to roughly 8-10 bits - making this AD9058 die a natural fit for 8-bit 50 MSPS applications where latency and bandwidth dominate over DC accuracy. Key specifications include 8-bit resolution, 50 MSPS sampling rate per channel, dual simultaneous sampling, parallel CMOS digital outputs, +5 V single-supply operation. The 5962- prefix indicates a DLA/DSCC Standard Microcircuit Drawing part number, which means the device has been through formal MIL-STD-883 Class B screening, including temperature cycling, hermeticity testing, and burn-in. Operating temperature range spans -55 C to +125 C. The AD9058 architecture uses two independent flash cores fed by wideband input buffers with track-mode bandwidth exceeding 175 MHz. The internal 2.5 V reference is resistor-ladder based and shared between both channels; an external reference override is supported for ratiometric or gain-trimmed operation. A separate output enable pin places the CMOS bus in high-impedance for multi-device sharing of a single parallel data bus. Typical applications include radar receiver IF digitizers, electronic-warfare front ends, transient-capture digitizers, military sonar baseband digitizers, and medical imaging front-ends (CT, ultrasound beam-formers). The wide analog input bandwidth (175 MHz) and low latency (one clock cycle) make the part well suited to time-interleaved IF sampling where phase coherency between channels is mandatory. When designing with this part, ensure the analog input is AC-coupled with a 50 ohm source termination to avoid degrading the wideband input stage; add a logic-supply decoupling network even though the part is single-supply, because the CMOS output drivers generate fast edge currents that couple back into the analog rails through the package lead frame. This page synthesizes DLA SMD cross-reference data, MIL-STD-883 screening information, and practical JLCC layout guidance not consolidated in any single distributor listing, providing engineers with a one-stop reference for hi-rel 8-bit dual-ADC design.

USD $195,00 En stock

5962-9851001NTB

5962-9851001NTB - Military FPGA, 22K Gates | AMD Xilinx

The 5962-9851001NTB is a high-performance Field Programmable Gate Array (FPGA) from AMD Xilinx, designed for demanding aerospace and defense applications. It features 1296 Configurable Logic Blocks (CLBs) and an equivalent gate count of 22,000, with a maximum usable gate count of 65,000. The device is packaged in a 240-pin FQFP (Fine-pitch Quad Flat Package) with gull-wing terminals, and operates over the full military temperature range of -55°C to +125°C. An FPGA (Field Programmable Gate Array) is an integrated circuit that can be configured by the customer after manufacturing to implement any digital logic function. FPGAs belong to the programmable logic device (PLD) family, which sits between fixed-function ASICs and general-purpose processors in the digital logic hierarchy. They offer reconfigurability, parallel processing, and rapid prototyping capabilities, making them essential in applications where flexibility and time-to-market are critical. Key features of the 5962-9851001NTB include its military temperature grade, high-reliability qualification to MIL-PRF-38535 QML, and a maximum clock frequency of 166 MHz. The device provides 3078 logic cells and supports a wide range of I/O standards, enabling integration with various system interfaces. The FQFP package offers a compact footprint with 0.5 mm pitch, suitable for space-constrained military electronics. Technically, the 5962-9851001NTB is based on Xilinx's mature FPGA architecture, featuring a sea-of-gates structure with configurable logic blocks interconnected by programmable routing. This architecture allows designers to implement complex digital systems, including state machines, DSP functions, and communication protocols. The device is supported by Xilinx's ISE design suite, which provides synthesis, place-and-route, and bitstream generation tools. Typical applications include military avionics, satellite communication systems, radar signal processing, and secure communication equipment. Its high reliability and extended temperature range make it suitable for harsh environments where commercial-grade components would fail. When designing with this FPGA, careful attention must be paid to power supply decoupling and signal integrity, as the high-speed I/O and internal logic can generate significant switching noise. Proper PCB layout with multiple ground planes and bypass capacitors is essential for reliable operation.

USD $90,00 En stock

5962L0423003VXC

5962L0423003VXC - 14-Bit 80MSPS ADC | MIL-PRF-38535 Class V | ADI

The Analog Devices 5962L0423003VXC is a 14-bit, 80 MSPS analog-to-digital converter (ADC) qualified to MIL-PRF-38535 Class V screening level, supplied in a 52-lead TQFP-EP package. Built on the proven AD6645 die, this military-grade ADC delivers high spurious-free dynamic range and low noise floor suitable for direct IF sampling in defense and aerospace signal chains. An analog-to-digital converter (ADC) is a data-conversion integrated circuit that converts a continuous analog input voltage or current into a discrete digital code proportional to the input magnitude. ADCs sit in the data-acquisition signal chain between the analog front end (amplifiers, filters, mixers) and the digital processor (FPGA, DSP, ASIC). Architectural variants include successive-approximation register (SAR), pipeline, flash, sigma-delta, and integrating converters; pipeline ADCs such as the 5962L0423003VXC dominate the 10 MSPS to 250 MSPS mid-speed segment where both sample rate and dynamic range matter. In the broader component taxonomy, the ADC belongs to the data-converter family, itself a subset of signal-conditioning and mixed-signal ICs under the broader power-management and analog-IC hierarchy. Key features of the 5962L0423003VXC include 14-bit resolution, 80 MHz minimum sample rate, dual 3.3 V/5 V analog supply, single 3.3 V or 5 V digital supply, integrated input buffer and track-and-hold, and LVDS/CMOS-compatible digital outputs. The -55 °C to +125 °C operating-temperature range and radiation-hardened-by-design construction (per the 5962 prefix SMD) make it appropriate for harsh-environment deployments. The internal architecture is based on a multi-stage pipeline core with proprietary input buffering that maintains distortion performance beyond 200 MHz IF. The hermetic ceramic TQFP-EP package (52 terminals) supports lead-bearing or lead-free finishes, with the EP providing a low-thermal-resistance path for high-temperature derating. On-chip dithering and gain trim yield consistent spurious-free dynamic range (SFDR) across lots, which is critical in radar and electronic-warfare receivers where repeatability under mission profile matters more than absolute best-case numbers. Typical applications include military radar receivers, electronic-countermeasures (ECM) front ends, software-defined radio (SDR) IF digitizers, satellite-communications (SATCOM) modems, and high-temperature industrial telemetry. The dual-supply topology simplifies interface to legacy 5 V analog signal chains still common in avionics, while the LVDS outputs ease hand-off to modern FPGAs and DACs. When designing around this part, note that the 52-pin TQFP-EP footprint requires a 4-layer PCB with a continuous ground plane under the exposed pad to meet the stated thermal and EMI performance. Decouple the AVCC and DVCC rails separately with 0.1 µF and 10 µF ceramics placed within 5 mm of each supply pin, and provide a well-bypassed external voltage reference for the best linearity. This page consolidates distributor stock, MIL-class-V screening documentation, and cross-reference information not found on a single manufacturer datasheet, giving procurement and design engineers a one-stop view of the 5962L0423003VXC for new defense and aerospace programs.

Devis En stock

5962R0423002VXC

5962R0423002VXC - 14-Bit 80MSPS Military ADC | Analog Devices

The Analog Devices 5962R0423002VXC is a MIL-PRF-38535-qualified 14-bit, 80 MSPS analog-to-digital converter (ADC) based on the AD6645 die, supplied in a 52-terminal ceramic GQFF (ceramic quad flat pack, FLAT terminal form) package. The SMD (Standardized Microcircuit Drawing) part-number prefix "5962R" indicates a Rad-tolerant, MIL-PRF-38535 Class V qualified device intended for harsh-environment and military electronic systems. Operating from a -55 °C to +125 °C military temperature range, the part converts wideband IF/RF analog signals into clean 14-bit digital words at sample rates up to 80 MSPS with on-chip CMOS-compatible outputs. An ADC (analog-to-digital converter) is a data-acquisition mixed-signal integrated circuit that samples a continuous analog input voltage and quantizes it into a discrete binary code; high-speed, high-resolution ADCs sit at the front end of receiver signal chains in radar, electronic warfare, software-defined radio, and digital instrumentation. ADCs of this family (Architecture: bipolar/CMOS pipeline) bridge the analog and digital subsystems and are part of the broader mixed-signal IC taxonomy that includes DACs, sample-and-hold amplifiers, and frequency converters. Key datasheet features of the AD6645 die behind this SMD include 14-bit resolution (no missing codes), an input bandwidth exceeding 200 MHz, a 75 dB SNR to 10 MHz analog input, and a 7.3 ENOB effective number of bits at Nyquist. The 5962R version adds 100 krad(Si) radiation tolerance and full MIL-PRF-38535 Class V processing, traceability, and screening, which are mandatory for flight hardware in defense and aerospace programs. The encoder uses a multi-stage pipelined architecture with an internal sample-and-hold and on-chip reference, providing low aperture jitter and excellent dynamic range for wideband IF sampling. Multiple ADCs of this family can be synchronized through an external encode clock, enabling coherent multi-channel receiver arrays. Typical applications include military radar IF receivers, electronic-counter-measures (ECM) digital receivers, satellite-communication (SATCOM) modems, SIGINT and ELINT front-ends, and high-end digital oscilloscope front-ends. The hermetic ceramic GQFF package supports both leaded through-hole and surface-mount-style reflow profiles qualified to MIL-STD-1835 and JEDEC standards. When designing with this SMD, follow MIL-PRF-38535 derating guidance (operate the part at 80% of maximum rated supply and clock to preserve reliability margin) and verify radiation-tolerance lot data against program requirements. Always check the Standardized Microcircuit Drawing (SMD) revision letter on each shipment against your qualified parts list.

USD $478,00 En stock

5AGXMA3D4F27I5G

5AGXMA3D4F27I5G - Arria V GX FPGA, 156K LE, 672-FCBGA | Intel

The Intel (formerly Altera) 5AGXMA3D4F27I5G is a member of the Arria V GX field-programmable gate array (FPGA) family, integrating approximately 156,000 logic elements, 11,746,304 bits of embedded memory, and 336 general-purpose I/Os in a 672-ball flip-chip BGA (FCBGA) package built on TSMC's 28 nm low-power process. Per the manufacturer part description, this industrial-temperature-grade device operates from a 1.1 V core supply and is offered in a 27 x 27 mm body with a 2.7 mm seated height, making it appropriate for space-constrained embedded systems. An FPGA (field-programmable gate array) is a semiconductor device whose digital logic fabric, interconnect, and I/O behavior are defined by user-supplied configuration data after manufacturing, allowing engineers to implement custom hardware pipelines, parallel processing engines, and interface bridges without an ASIC NRE. FPGAs sit at the top of the programmable-logic taxonomy (programmable logic device -> FPGA -> SRAM-based FPGA -> Arria V family) and compete against microcontrollers, DSPs, and GPUs in latency-sensitive and high-throughput workloads. Key feature highlights of 5AGXMA3D4F27I5G include 156,000 logic elements organized in adaptive logic modules (ALMs), 8 integrated transceivers suitable for multi-gigabit serial links, hard memory controllers, and PCIe Gen2 hard IP blocks. The integrated transceivers support protocols such as PCIe Gen1/Gen2, Gigabit Ethernet, CPRI, and Serial RapidIO, reducing external PHY cost. The flip-chip BGA package provides low-inductance power delivery and superior thermal performance for industrial-temperature operation from -40C to +100C. Architecturally, the Arria V GX uses a logic-economy fabric with 8-input fracturable look-up tables, embedded DSP blocks (each capable of 18x18 or 27x27 multiply-accumulate), and 10.6 Mbit of embedded memory per tile. Configuration is loaded through JTAG, serial flash, or passive parallel interfaces, with bitstream encryption and design-security features available. Typical applications include industrial machine vision and video processing cards, telecom baseband pre-processing, military/aerospace signal processing, and PCIe-based coprocessor cards. The Arria V GX balances transceiver count, logic density, and power for mid-range embedded designs. When designing with this part, plan power-sequencing for the 1.1 V core, 2.5 V/3.3 V auxiliary, and transceiver supplies, and follow Intel's pin-out guidelines for the F27 672-ball package to avoid signal-integrity issues on high-speed serial links. This page synthesizes distributor pricing, the most current 5AGXMA3D4F27I5G inventory data, same-family alternatives, and practical design notes not found in the manufacturer datasheet alone.

USD $580,25 En stock

5AGXMA3D4F31I5G

5AGXMA3D4F31I5G - Arria V GX FPGA, 156K LE, 11.7Mbit, 896-FCBGA | Altera

The Altera 5AGXMA3D4F31I5G is a 156,000-logic-element Arria V GX Field-Programmable Gate Array (FPGA) from the 5AGXA3 F31 device family, built on a 28 nm process and packaged in a 896-ball FineLine Ball-Grid Array (FC-FBGA). It integrates 11,746,304 bits of embedded memory, 416 maximum user I/O, and 24 transceiver channels compliant with the Arria V GX transceiver architecture, operating from a 1.1 V core supply across the industrial temperature range. An FPGA (Field-Programmable Gate Array) is a reconfigurable semiconductor device containing an array of programmable logic blocks, interconnect, I/O cells, and - in modern families - dedicated hard IP such as transceivers, DSP blocks, and embedded memory. FPGAs sit above fixed-function ASICs and microcontrollers in flexibility and below them in per-unit cost for high volumes, and they occupy a critical tier of the broader programmable logic / semiconductor hierarchy alongside CPLDs and SoC FPGAs. The Arria V GX family specifically targets mid-range applications where transceivers, DSP throughput, and modest power are required. The 5AGXMA3D4F31I5G features 156,000 logic elements, 11,746,304 embedded memory bits, integrated PCI Express Gen2 hard IP, and 24 high-speed transceiver channels supporting protocols such as CPRI, OBSAI, Serial RapidIO, and 10 Gbps backplane. The 28 nm low-power process delivers an attractive performance-per-watt profile for transceiver-rich designs, while the 896-ball FCBGA package exposes 416 user I/O pins. Architecturally, the device combines a hardened transceiver PHY, embedded PCIe Gen2 endpoint blocks, variable-precision DSP blocks, and 8-input adaptive logic modules (ALMs) feeding into a multi-tier routing fabric. The I suffix indicates an industrial temperature grade (-40C to +100C), and the 5 in the speed grade position places it in the speed-grade-5 device bin. Quartus II / Quartus Prime is the design entry and timing-analysis toolchain. Typical applications include wireless baseband processing, software-defined radio, broadcast video infrastructure, industrial machine vision, radar preprocessing, and high-speed serial protocol bridging. The combination of integrated transceivers, PCIe Gen2, and substantial DSP makes it well-suited to telecom infrastructure and high-performance test equipment. When designing, allocate adequate PCB layers for the 896-ball FCBGA break-out, follow Altera's transceiver reference design guidelines for channel reach, and validate thermal solutions against the industrial-grade junction envelope. Designers should also verify Quartus Prime version support for the specific speed grade. This page synthesizes distributor pricing, Arria V GX family variants, drop-in same-package options, and practical design notes not found in the manufacturer datasheet alone.

USD $1 145,00 En stock

5AGXMA3D4F31I5N

5AGXMA3D4F31I5N - Arria V GX FPGA, 156K LE, 896-FCBGA | Intel

The Intel (formerly Altera) 5AGXMA3D4F31I5N is a member of the Arria V GX family of mid-range FPGAs, integrating 156000 logic elements, 11746304 bits of embedded memory, and 416 user I/Os in a 896-ball FCBGA package. The device is built on TSMC's 28nm process technology and operates at a core voltage of 1.1V, with the industrial temperature grade (-40C to +100C) encoded in the part suffix. A field-programmable gate array (FPGA) is a reconfigurable semiconductor device containing an array of programmable logic blocks, interconnect, and I/O cells that the engineer can customize after manufacturing. FPGAs sit between fixed-function ASICs (high NRE, high volume) and software-defined processors (fixed hardware, sequential) in the silicon hierarchy: FPGA -> programmable logic -> reconfigurable computing -> semiconductor. The Arria V GX specifically targets applications requiring high-speed serial transceivers, embedded hard IP blocks, and balanced logic/memory/DSP resources. Key features of the 5AGXMA3D4F31I5N include 5890 logic array blocks (LABs) per the Mouser product summary, integrated PCIe hard IP, up to 9.225 Gbps transceivers, and dedicated DSP blocks for high-throughput signal processing. The 896-ball FCBGA package supports 416 user I/Os with high-speed serial lanes grouped along dedicated banks, allowing simultaneous DDR3 memory interfacing and multi-gigabit serial links. Architecturally, the Arria V GX combines a hard PCIe Gen2 endpoint, hard memory controllers, and up to 36 transceiver channels at data rates suitable for 10G Ethernet, CPRI, and 3G-SDI backhaul. The 28nm process balances static and dynamic power versus cost-per-logic, and the I5 speed grade indicates the slowest commercially available timing closure window, chosen for power-sensitive industrial designs. Typical applications include 10G Ethernet aggregation switches, wireless baseband processing (CPRI/OBSAI fronthaul), military and industrial video processing pipelines, and PCI Express endpoint cards in test/measurement. The part is frequently designed into long-life-cycle embedded systems where an ASIC redesign is economically infeasible. When laying out the 896-FCBGA, allocate a 31mm x 31mm BGA land pattern with microvia stacking for breakout; signal integrity demands reference planes for every transceiver lane. The device requires multiple decoupling rails (0.9V, 1.1V, 1.8V, 2.5V, 3.3V) and a programmable clock tree managed by the Intel Quartus Prime toolchain. This page synthesizes 16-distributor price comparison, parametric side-by-side with same-family Arria V GX alternatives, and PCB design guidance beyond what is found in the manufacturer datasheet.

USD $1 390,00 En stock

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5962-0423001QXC - 14-Bit 80 MSPS Military ADC QML Q | Analog Devices

5962-85127023A - 12-Bit SAR ADC, 28-LCC | Analog Devices

5962-8871901MXA - 12-Bit Quad DAC, 28-CDIP | Analog Devices

5962-8965501LA - 12-Bit Military ADC | Analog Devices

5962-9078501MLA - 12-Bit Dual DAC, MIL-STD-883 | Analog Devices

5962-9169003M3A - 12-Bit SAR ADC, 28-LCC | Analog Devices

5962-9470301MYA - 8-Bit 50MSPS Dual Flash ADC | ADI | MIL-STD-883

5962-9851001NTB - Military FPGA, 22K Gates | AMD Xilinx

5962L0423003VXC - 14-Bit 80MSPS ADC | MIL-PRF-38535 Class V | ADI

5962R0423002VXC - 14-Bit 80MSPS Military ADC | Analog Devices

5AGXMA3D4F27I5G - Arria V GX FPGA, 156K LE, 672-FCBGA | Intel

5AGXMA3D4F31I5G - Arria V GX FPGA, 156K LE, 11.7Mbit, 896-FCBGA | Altera

5AGXMA3D4F31I5N - Arria V GX FPGA, 156K LE, 896-FCBGA | Intel