EP1810JM-45 vs EP1810GM883 比較

詳細な並列比較: EP1810JM-45 メーカー: Altera および EP1810GM883 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EP1810JM-45 EP1810GM883
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $14.20 $175.00
Device Family Classic EPLD (EP1810 series) —
Macrocells 48 48
Usable Gates ~900 gates —
Propagation Delay (tpd) 45 ns (max, -45 speed grade) 45 ns (max)
Supply Voltage (VCC) 4.5 V to 5.5 V —
Technology CMOS, UV-EPROM configuration —
Package Type JLCC-68 (ceramic J-leaded chip carrier) —
Package Code JM (windowed ceramic, UV-erasable) —
ピン数 68 —
動作温度 -55 C to +125 C (military grade) -55C to +125C (MIL-STD-883 Class B)
I/O Compatibility CMOS / TTL —
Configuration Method JEDEC fuse map, EPROM programmer —
Programming Technology UV-erasable EPROM (non-volatile, instant-on) —
実装タイプ Surface Mount (J-lead) Through-Hole (PGA socket)
Logic Type EPLD / PLD (programmable logic device) —
RoHS ステータス [DATA_NEEDED: RoHS status - legacy mil-spec part] [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data]
MSLレベル [DATA_NEEDED: MSL level] —
Family — Classic EPLD (EP1810 series)
Device Type — UV-Erasable Programmable Logic Device (EPLD)
Dedicated Inputs — 12
User I/O Pins — 48
Total Terminals — 68
Global Clocks — 4
Supply Voltage (Vcc) — 4.5 V to 5.5 V (nominal 5 V)
Maximum Toggle Frequency (fmax) — [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade]
Process Technology — CMOS, UV-erasable
パッケージ — 68-Pin Ceramic Pin Grid Array (PGA)
Screening — MIL-STD-883 Class B (suffix '883' denotes MIL processing)
Lead-Free — [DATA_NEEDED: military 883B screened parts commonly use SnPb finish]

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