EP20K600CF33C9 vs EP20K600CF33C8N Comparaison
Comparaison détaillée côte à côte de EP20K600CF33C9 par Intel et EP20K600CF33C8N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K600CF33C9 | EP20K600CF33C8N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $171,00 | $162,75 |
| Family | APEX 20KC | APEX 20KC |
| Process Technology | 0.15 µm CMOS | — |
| System Gates | 600,000 (maximum) | — |
| Logic Elements / Cells | 24,320 | 24,320 |
| Maximum Operating Frequency | 250 MHz | — |
| Fréquence d'horloge maximale | 303.03 MHz | — |
| Propagation Delay | 2.0 ns | — |
| Core Supply Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | — |
| User I/O | 588 (4 dedicated inputs + 580 general-purpose I/O) | — |
| Boîtier | 1020-ball FC-FBGA | 1020-pin FC-FBGA (flip-chip) |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Embedded RAM | Dual-port RAM blocks (per family) | — |
| Programmability | JTAG / IEEE 1149.1 ISP, SRAM-based | — |
| Statut RoHS | [DATA_NEEDED: rohs status] | Compliant (N suffix) |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Logic Block Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| I/O Standards Supported | LVTTL, LVCMOS, LVDS (per family datasheet) | — |
| Total RAM Bits | — | 311,296 |
| Number of LABs / CLBs | — | 2,432 |
| Number of Gates | — | 1,537,000 (max) |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Core Voltage Supply | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Technology / Process | — | 0.15 µm CMOS |
| Maximum Internal Frequency | — | 301.21 MHz |
| Speed Grade | — | -8 (slower than -7) |
| Température de fonctionnement | — | 0°C to 85°C (TJ) |
| Pitch | — | 0.33 mm |
| Programmable Type | — | In-System / SRAM-based |
| Configuration Interface | — | JTAG (IEEE 1149.1) + Passive Serial / Parallel |