EP910PI-35T vs EP910PI-30T Comparaison
Comparaison détaillée côte à côte de EP910PI-35T par Altera et EP910PI-30T par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910PI-35T | EP910PI-30T |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $11,15 | $10,95 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 480 |
| Pin-to-Pin Logic Delay (tpd) | 35 ns | — |
| Counter Frequency (fCNT) | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| I/O Logic Compatibility | 100% TTL emulation | — |
| Process Technology | CMOS | — |
| Boîtier | 40-pin PDIP (Plastic DIP) | — |
| Type de montage | Through-Hole | Through-Hole |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (industrial) |
| Programming Method | UV-erasable, EPROM technology | — |
| On-board Test Circuitry | Yes (logic test mode for AC verification) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Dedicated Inputs | — | 10 |
| Propagation Delay (tPD) | — | 30 ns |
| Register (Clock-to-Output) Delay | — | 20 ns |
| Technology | — | CMOS, UV-erasable (windowed ceramic) |
| Package Type | — | 40-pin PDIP (ceramic windowed) |
| Programming | — | Altera Classic device programmer / MAX+PLUS II flow |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |