EP910PI-35T vs EP910PI-30T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-35T sa pamamagitan ng Altera at EP910PI-30T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-35T | EP910PI-30T |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 480 |
| Pin-to-Pin Logic Delay (tpd) | 35 ns | — |
| Counter Frequency (fCNT) | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| I/O Logic Compatibility | 100% TTL emulation | — |
| Process Technology | CMOS | — |
| Packhaging | 40-pin PDIP (Plastic DIP) | — |
| Uri ng Pagpapasok | Through-Hole | Through-Hole |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (industrial) |
| Programming Method | UV-erasable, EPROM technology | — |
| On-board Test Circuitry | Yes (logic test mode for AC verification) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Dedicated Inputs | — | 10 |
| Propagation Delay (tPD) | — | 30 ns |
| Register (Clock-to-Output) Delay | — | 20 ns |
| Technology | — | CMOS, UV-erasable (windowed ceramic) |
| Package Type | — | 40-pin PDIP (ceramic windowed) |
| Programming | — | Altera Classic device programmer / MAX+PLUS II flow |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |