EPC1LI20 vs EPC1PCB Comparaison
Comparaison détaillée côte à côte de EPC1LI20 par Altera et EPC1PCB par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC1LI20 | EPC1PCB |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | Memory ICs | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,50 | $9,60 |
| Type de mémoire | OTP Configuration PROM (EPROM-based) | — |
| Taille de mémoire | 1 Mb (1,048,576 bits) | — |
| Configuration Interface | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) | — |
| Maximum Configuration Clock | 8 MHz | — |
| Supply Voltage (VCC) | 5.0 V (4.75 V to 5.25 V) | — |
| Programming Voltage (VPP) | 12.75 V (typical, factory-programmed via JTAG) | — |
| Boîtier | 20-pin PLCC (J-lead, 9x9 mm) | PLCC-20 (Plastic Leaded Chip Carrier) |
| Nombre de broches | 20 | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Cascading Support | Yes (nCASC pin for multi-device daisy chain) | — |
| Endurance | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) | — |
| JTAG Programming | Yes (in-system via IEEE 1149.1) | — |
| Compatible FPGA Families | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury | — |
| Type de montage | Surface Mount (PLCC socket compatible) | Surface Mount (socket-compatible) |
| Niveau MSL | 1 (per Partstack datasheet record) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] | [DATA_NEEDED: lead-free/RoHS status] |
| Product Type | — | Enhanced Configuration Device for SRAM-based FPGAs |
| Memory Density | — | 1 Mbit |
| Program Memory Type | — | Flash (non-volatile) |
| Configuration Modes Supported | — | FPP (Fast Passive Parallel), PS (Passive Serial) |
| Supply Voltage VCC | — | 3.3 V |
| I/O Voltage Tolerance | — | 5.0 V tolerant |
| Supported FPGA Families | — | APEX, FLEX, ACEX, Cyclone, Stratix |
| Interface | — | Altera configuration bus (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Multi-Device Daisy Chain | — | Yes (nCASC, nCS pins) |
| Programming Interface | — | JTAG (IEEE 1149.1 boundary scan) |
| In-System Programmable | — | Yes |
| Program/Erase Endurance | — | [DATA_NEEDED: program/erase cycles] |
| Data Retention | — | [DATA_NEEDED: data retention years] |