EPC1LI20 vs EPC1PCB Comparação
Comparação detalhada lado a lado de EPC1LI20 por Altera e EPC1PCB por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPC1LI20 | EPC1PCB |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | Memory ICs | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | NRND |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $8,50 | $9,60 |
| Tipo de memória | OTP Configuration PROM (EPROM-based) | — |
| Tamanho da memória | 1 Mb (1,048,576 bits) | — |
| Configuration Interface | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) | — |
| Maximum Configuration Clock | 8 MHz | — |
| Supply Voltage (VCC) | 5.0 V (4.75 V to 5.25 V) | — |
| Programming Voltage (VPP) | 12.75 V (typical, factory-programmed via JTAG) | — |
| Encapsulamento | 20-pin PLCC (J-lead, 9x9 mm) | PLCC-20 (Plastic Leaded Chip Carrier) |
| Contagem de pinos | 20 | — |
| Temperatura de operação | [DATA_NEEDED: operating temperature range] | — |
| Cascading Support | Yes (nCASC pin for multi-device daisy chain) | — |
| Endurance | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) | — |
| JTAG Programming | Yes (in-system via IEEE 1149.1) | — |
| Compatible FPGA Families | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury | — |
| Tipo de montagem | Surface Mount (PLCC socket compatible) | Surface Mount (socket-compatible) |
| Nível MSL | 1 (per Partstack datasheet record) | — |
| Status RoHS | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] | [DATA_NEEDED: lead-free/RoHS status] |
| Product Type | — | Enhanced Configuration Device for SRAM-based FPGAs |
| Memory Density | — | 1 Mbit |
| Program Memory Type | — | Flash (non-volatile) |
| Configuration Modes Supported | — | FPP (Fast Passive Parallel), PS (Passive Serial) |
| Supply Voltage VCC | — | 3.3 V |
| I/O Voltage Tolerance | — | 5.0 V tolerant |
| Supported FPGA Families | — | APEX, FLEX, ACEX, Cyclone, Stratix |
| Interface | — | Altera configuration bus (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Multi-Device Daisy Chain | — | Yes (nCASC, nCS pins) |
| Programming Interface | — | JTAG (IEEE 1149.1 boundary scan) |
| In-System Programmable | — | Yes |
| Program/Erase Endurance | — | [DATA_NEEDED: program/erase cycles] |
| Data Retention | — | [DATA_NEEDED: data retention years] |