EPC22C20N vs EPC21LC20 Comparaison
Comparaison détaillée côte à côte de EPC22C20N par Altera et EPC21LC20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC22C20N | EPC21LC20 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $11,40 | $10,40 |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | Configuration PROM for SRAM-based LUT FPGAs | — |
| Target FPGA Family | FLEX 10K, FLEX 6000, APEX 20K series | — |
| Configuration Interface | Serial (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) | — |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | IEEE 1149.1 (JTAG) |
| Tension d'alimentation | 3.3 V or 5 V | — |
| Boîtier | 20-pin PLCC (J-lead) | — |
| Package Marking Code | EPC22C20N | — |
| Nombre de broches | 20 | — |
| Type de montage | Surface Mount / Socket | Surface Mount (PLCC socket or solder) |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Bitstream Capacity | [DATA_NEEDED: bitstream capacity in bits] | — |
| Configuration Time | [DATA_NEEDED: typical configuration time] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm from Altera product page] |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Statut du cycle de vie | Obsolete (last-time-buy from Altera announced for legacy configuration devices) | — |
| Type de mémoire | — | Serial Configuration PROM (Flash-based, in-system programmable) |
| Density | — | 2 Mb (2,097,152 bits) |
| Configuration Mode Supported | — | Serial (PS) for Altera SRAM-based LUT FPGAs |
| Maximum DCLK Frequency | — | 10 MHz |
| Access Time | — | approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure] |
| Program/Erase Endurance | — | 100 cycles minimum [DATA_NEEDED: confirm from datasheet] |
| Operating Voltage (VCC) | — | 3.0 V to 3.6 V (3.3 V typical) |
| Standby Current | — | [DATA_NEEDED: ICCSB value] |
| Active Read Current | — | [DATA_NEEDED: ICC active current] |
| Operating Temperature (commercial) | — | 0 °C to +70 °C (LC suffix) |
| Operating Temperature (industrial) | — | [DATA_NEEDED: -40 to +85 °C for LI variant] |
| Boîtier / Format | — | 20-pin PLCC (J-lead, JEDEC MS-018) |
| Niveau MSL | — | [DATA_NEEDED: confirm moisture sensitivity level] |
| Lead-Free (Pb-free) | — | [DATA_NEEDED: confirm] |
| Compatible FPGA Families | — | ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT) |
| JTAG Boundary-Scan Compliant | — | Yes (IEEE Std 1149.1) |
| Data Width | — | 1 bit (serial DATA output) |