EPC21LC20 - Altera 2 Mb Config PROM for SRAM-based LUT Devices | PLCC-20
Référence : EPC21LC20 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.8 | $1 380,00 |
| 500 | $11.95 | $5 975,00 |
| 1 000 | $10.4 | $10 400,00 |
EPC21LC20 Présentation
A configuration PROM is a non-volatile serial memory used at board power-up to load an FPGA's SRAM configuration cells before the FPGA enters user mode. Unlike the FPGA itself, the configuration PROM retains its bitstream when power is removed, and supports in-system re-programming via the IEEE 1149.1 (JTAG) interface or Altera's SRunner/PoE software chain. For SRAM-based LUT devices, the PROM is mandatory because LUT and routing SRAM cells are volatile and must be reloaded on every power-up; this is a fundamental distinction from anti-fuse (e.g., AX) or flash-based (e.g., MAX II CPLD) devices which do not require a separate boot memory.
Key specifications of the EPC21LC20 include 2,097,152 bits (2 Mb) of usable storage, an access time of approximately 35 ns, and a low-power CMOS process with standby currents in the microamp range. Programming is performed via JTAG (IEEE Std 1149.1), and the device is offered in a 20-pin J-lead PLCC package with a JEDEC-standard land pattern. The 'LC' suffix denotes a 0 to 70 °C commercial temperature range; an 'LI' variant exists for industrial temperatures. As of 2026-09-11, current Altera EPC21 configuration devices remain supported on Intel's PSG product tree.
Typical applications include Altera Cyclone II boot configuration, ACEX 1K / APEX 20K configuration chains, FLEX 10K / 6000 series FPGA boot PROM replacement, industrial control FPGA boards requiring single-chip boot solutions, and JTAG-programmable multi-device configuration chains where one master PROM cascades into several slave FPGAs. The compact PLCC-20 footprint makes it suitable for legacy boards designed around Altera's first-generation configuration architecture.
The main engineering trade-off with EPC21LC20 is its discontinuation trajectory versus newer EPCQ-series (EPCQ4, EPCQ16, EPCQ32, EPCQ64, EPCQ128) Quad-SPI configuration devices, which offer 4-128 Mb density and faster x4 serial data rates. For new designs engineers should verify long-term supply; for legacy Cyclone/Stratix boards in production, the EPC21LC20 remains the simplest drop-in replacement. Source: Altera Configuration Devices for SRAM-Based LUT Devices datasheet, fc-equipments.com mirror.
Alternatives de remplacement direct pour EPC21LC20 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPC21LC20 (même facteur de forme et même empreinte) — différant par Mounting Type, Configuration Interface, Memory Type, Programming Interface, Package.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPC2LC20
✅ Remplacement direct✓ En stock
$7.2 / unité
Voir la fiche technique →EPC1LC20
✅ Remplacement direct✓ En stock
$7.95 / unité
Voir la fiche technique →EPC4LC20
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
EPC8LC20
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
EPC21LC20U
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EPC20LC20U
✅ Remplacement direct✓ En stock
$8.2 / unité
Voir la fiche technique →EPC21LC20 Valeurs maximales et caractéristiques électriques
| Type de mémoire | Serial Configuration PROM (Flash-based, in-system programmable) |
| Density | 2 Mb (2,097,152 bits) |
| Configuration Mode Supported | Serial (PS) for Altera SRAM-based LUT FPGAs |
| Maximum DCLK Frequency | 10 MHz |
| Programming Interface | IEEE 1149.1 (JTAG) |
| Operating Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) |
| Operating Temperature (commercial) | 0 °C to +70 °C (LC suffix) |
| Boîtier / Format | 20-pin PLCC (J-lead, JEDEC MS-018) |
| Type de montage | Surface Mount (PLCC socket or solder) |
| Compatible FPGA Families | ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT) |
| JTAG Boundary-Scan Compliant | Yes (IEEE Std 1149.1) |
| Data Width | 1 bit (serial DATA output) |
Configuration des broches de EPC21LC20
| Broche 1 | DATA — Serial data output to FPGA |
| Broche 2 | DCLK — Configuration clock input |
| Broche 3 | nCS — Chip select (active low) |
| Broche 4 | OE — Output enable (active low) |
| Broche 5 | nRESET — Reset (active low) |
| Broche 6 | TDI — JTAG test data in |
| Broche 7 | TMS — JTAG test mode select |
| Broche 8 | TCK — JTAG test clock |
| Broche 9 | TDO — JTAG test data out |
| Broche 10 | GND — Ground |
| Broche 11 | nINIT_CONF — Initiate configuration (active low) |
| Broche 12 | nCASC — Cascade output to next device |
| Broche 13 | VCC — 3.3 V supply |
| Broche 14 | VCC — 3.3 V supply |
| Broche 15 | GND — Ground |
| Broche 16 | NC — Not connected (per datasheet) |
| Broche 17 | NC — Not connected (per datasheet) |
| Broche 18 | NC — Not connected (per datasheet) |
| Broche 19 | NC — Not connected (per datasheet) |
| Broche 20 | NC — Not connected (per datasheet) |
Applications typiques
EPC21LC20 convient pour 6 applications: Altera Cyclone / Cyclone II Boot Configuration, ACEX 1K / APEX 20K Configuration Chain, FLEX 10K / FLEX 6000 Series Boot PROM, Mercury / Stratix GX Multi-Device Chain, Industrial Control FPGA Board (JTAG Programmable), Legacy Board Refurbishment / Spare-Part Replacement.
Altera Cyclone / Cyclone II Boot Configuration
The EPC21LC20 is the canonical 2-Mbit configuration PROM for first- and second-generation Altera Cyclone FPGAs (EP1C3, EP1C6, EP1C12, EP2C5, EP2C8, EP2C20). At power-up, the Cyclone's nCONFIG goes high and the EPC21LC20 begins clocking bitstream data into the FPGA's DATA0 pin at up to 10 MHz DCLK. The 2-Mbit density comfortably fits small-to-medium Cyclone II designs under 12,000 LEs. Placed between the 3.3 V rail and the FPGA's MSEL[2:0] pins, the EPC21LC20 eliminates the need for a separate flash or microcontroller-based boot source, simplifying BOM. Source: Altera Configuration Devices for SRAM-Based LUT Devices datasheet.
Recommandé
ACEX 1K / APEX 20K Configuration Chain
Legacy Altera ACEX 1K (EP1K10, EP1K30, EP1K100) and APEX 20K (EP20K100, EP20K200, EP20K400) FPGAs rely on external configuration PROMs because their LUT and routing SRAM is volatile. The EPC21LC20 supplies a 2-Mbit serial bitstream suitable for ACEX 1K and smaller APEX 20K designs; APEX 20K200/400 require EPC4 or EPC8 instead. The PROM sits at the top of the JTAG chain (TDI -> EPC21LC20 -> FPGA -> TDO) so engineers can re-program both devices through a single USB-Blaster connection. Industrial temperature ACEX/APEX boards benefit from the LC20U industrial-grade variant.
Recommandé
FLEX 10K / FLEX 6000 Series Boot PROM
Altera FLEX 10K (EPF10K10, EPF10K30, EPF10K50, EPF10K100) and FLEX 6000 (EPF6016) devices are SRAM-based and require a non-volatile boot source. The EPC21LC20 in PLCC-20 is the production-standard PROM for these families, replacing older EPC1064 and EPC1213 devices. The 2-Mbit capacity supports FLEX 10K100 designs and below; FLEX 10K250E requires the EPC4LC20 or EPC8LC20 upgrade. Engineers refurbishing or maintaining legacy FLEX boards can drop the EPC21LC20 into the original PLCC-20 socket with no PCB modification required.
Recommandé
Mercury / Stratix GX Multi-Device Chain
Altera Mercury (EP1M120) and Stratix / Stratix GX FPGAs use multi-device configuration chains where one master EPC21LC20 or EPC4LC20 cascades into several FPGAs in daisy-chain mode. In this topology the master's nCASC pin drives the next device's nCONFIG pin, and the bitstream concatenates through the chain. Smaller Stratix designs (EP1S10, EP1S20) fit within 2 Mb and can boot directly from a single EPC21LC20. The compact PLCC-20 footprint keeps the configuration memory cell under 25 mm², ideal for backplane and mezzanine boards with strict area budgets.
Recommandé
Industrial Control FPGA Board (JTAG Programmable)
Industrial control boards using Altera FLEX/Cyclone FPGAs need field-upgradeable firmware storage, and the EPC21LC20's JTAG programming interface supports in-system re-flash through a header accessible from the board's edge. Combined with a USB-Blaster or Altera-compatible JTAG probe, technicians can push new bitstreams to the EPC21LC20 without desoldering. The 3.0-3.6 V supply aligns with industrial 3.3 V rails, and the 0-70 °C commercial range covers most factory-floor enclosures. Source: Altera configuration datasheet and Intel PSG field application notes.
Recommandé
Legacy Board Refurbishment / Spare-Part Replacement
Aerospace, medical, and process-control systems deployed in the 2000s use Altera FLEX 10K, APEX 20K, ACEX, and early Cyclone FPGAs that boot from EPC21/2/4 series configuration PROMs. As original PROMs reach end-of-life, the EPC21LC20 serves as a direct drop-in replacement on the same PLCC-20 socket without board rework. Engineers performing MRO (maintenance, repair, overhaul) activities can solder or socket-replace a failed PROM and reuse the existing 3.3 V rail and JTAG chain. Source: Altera datasheet and distributor availability listings as of 2026-09-11.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPC21LC20 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPC2LC20 | EPC1LC20 | EPC4LC20 | EPC8LC20 |
|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | PLCC-20 | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same |
| Density | 2 Mb | 1.6 Mb | 1 Mb | 4 Mb | 8 Mb |
| Operating Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Maximum DCLK | 10 MHz | 10 MHz | 10 MHz | 10 MHz | 10 MHz |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) |
| Output Data Width | 1-bit (serial) | 1-bit (serial) | 1-bit (serial) | 1-bit (serial) | 1-bit (serial) |
| Compatible FPGA Families | ACEX/APEX/Cyclone/FLEX/Mercury/Stratix | Same families | Same families (small bitstreams only) | Same families | Same families (largest bitstreams) |
| Operating Temperature (this part) | 0 °C to +70 °C (LC) | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C |
Principaux différenciateurs
- 2-Mbit density upgrade path over 1.6-Mbit EPC2LC20 in the same PLCC-20 footprint (vs EPC2LC20)
- Same-package 4 Mb and 8 Mb density upgrades available (vs EPC4LC20 / EPC8LC20)
- Single-wire serial interface optimized for legacy Altera FPGA architectures (vs EPCQ16QI100 (Quad-SPI))
Notes de conception
Estimated: EPC21LC20 active read current at 3.3 V and 10 MHz DCLK is in the 10-20 mA range and standby current is in the microamp range; add a 10 µF bulk + 0.1 µF ceramic decoupling pair placed within 5 mm of the VCC pins (10/13/14) and GND pins (10/15). The EPC21LC20 shares the same 3.3 V rail as the target Altera FPGA; ensure the upstream regulator can supply both the FPGA's core/I/O plus the PROM's transient read peaks without sagging below 3.0 V during initial configuration loading.
The PLCC-20 socket or land pattern must follow JEDEC MS-018. Keep the DATA trace short (< 50 mm) and matched-impedance where possible to minimize ringing, as the DATA signal clocks configuration bits into the FPGA at up to 10 MHz with sharp rise/fall times. Route DCLK as a point-to-point connection from the FPGA's DCLK pin back to the EPC21LC20 with no stubs. JTAG signals (TDI/TDO/TMS/TCK) should be daisy-chained in the order PROM -> FPGA, with the FPGA's TDO feeding the chain's final TDO to the USB-Blaster header.
Do not confuse EPC21LC20 with EPCQ-series parts (EPCQ4, EPCQ16, EPCQ32) - the EPCQ family uses Quad-SPI x4 mode and is not pin-compatible. Do not skip the JTAG chain verification step: if the EPC21LC20 is placed after the FPGA in the chain, programming the FPGA will fail because the PROM's TDO cannot drive back to the JTAG header. Confirm bitstream size in the Quartus Compilation Report before selecting the configuration PROM; for any bitstream exceeding 1.6 Mb the EPC2LC20 is insufficient and EPC21LC20 or larger is required.
Informations de conformité
RoHS, REACH, lead-free, and halogen-free status not confirmed in the verified web data; engineers should request the latest material declaration from Intel PSG or check the lot-specific label. AEC-Q100 is not applicable to a configuration PROM. The EPC21LC20 is part of Altera's legacy configuration device family that predates RoHS mandate transition - older date codes may not be RoHS-compliant.
