EPC2LS20U vs EPC1LC20 比較
詳細並排比較 EPC2LS20U 由 Altera 與 EPC1LC20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LS20U | EPC1LC20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | In-System Programmable Configuration PROM | — |
| Memory Density | 1.6 Mbit | — |
| Operating Voltage (VCC) | 3.3 V | — |
| 介面 | Altera serial configuration / JTAG | — |
| Programming Method | In-System Programmable (ISP) via JTAG | — |
| 封裝 | 20-PLCC (J-lead, 9x9 mm) | 20-pin PLCC (J-leaded, surface mount) |
| Lead-Free / RoHS | Yes (per "U" suffix) | — |
| 工作溫度 | [DATA_NEEDED: Operating Temperature] | [DATA_NEEDED: Operating temperature range] |
| Supported FPGA Families | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 | — |
| Configuration Modes | PS (Passive Serial), AS, FPP | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | — |
| Done Pin | Yes (open-drain programmable polarity) | — |
| nSTATUS Pin | Yes (open-drain error flag) | — |
| nCONFIG Pin | Yes (reset/reconfiguration input) | — |
| DCLK Output | Yes (configuration clock to FPGA) | — |
| MSL 等級 | [DATA_NEEDED: MSL Level] | — |
| Compliance | RoHS (Pb-free per U suffix) | — |
| 記憶體類型 | — | Non-volatile configuration memory (Flash/EPROM) |
| Memory Capacity | — | 1 Mbit (1,048,576 bits) |
| 介面類型 | — | Serial configuration interface |
| Maximum DCLK Frequency | — | 8 MHz |
| 供應電壓 | — | 3.3 V or 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 / JTAG) |
| Programmable Voltage | — | 5.0 V and 3.3 V ISP |
| Configuration Mode | — | Serial, multi-device daisy-chain capable |
| 腳位數 | — | 20 |
| 安裝類型 | — | Surface Mount |
| Compatible FPGA Families | — | ACEX 1K, APEX 20K, FLEX 10K, Cyclone, Mercury |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status] |
| JTAG Pins | — | TCK, TMS, TDI, TDO |