EPM5128JC vs EPM5064JC-1 Comparaison
Comparaison détaillée côte à côte de EPM5128JC par Altera et EPM5064JC-1 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5128JC | EPM5064JC-1 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $18,25 |
| Product Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Logic Elements | Programmable AND/OR/XOR array | 128 (Logic Array Blocks) |
| Supply Voltage (VCC) | 5 V (typical) | 5 V nominal (4.75 V – 5.25 V) |
| Nombre de broches | 68 | — |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | — |
| Dedicated Inputs | 8 | [DATA_NEEDED: dedicated input count] |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Configuration Memory | UV-erasable EPROM (windowed package) | — |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | — |
| Température de fonctionnement | Commercial 0C to +70C | 0 °C to +70 °C (commercial, -JC suffix) |
| Type de montage | Surface Mount (PLCC socket or solder) | Surface Mount (PLCC socket recommended) |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | — |
| Process Technology | CMOS EPROM | 0.8 µm CMOS |
| Statut RoHS | [DATA_NEEDED: RoHS status - legacy part] | Non-compliant (windowed ceramic, contains Pb in glass frit) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 |
| Macro Cells | — | 64 |
| Usable Gates | — | 1250 (typical) |
| Maximum Operating Frequency | — | 33.3 MHz (fCNT) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD typical/max in ns] |
| Programmable Pins | — | 36 (typical I/O, 44-pin PLCC) |
| Boîtier | — | 44-pin PLCC (J-lead, windowed ceramic) |
| Erasure Method | — | UV-erasable through quartz window |
| Programming Method | — | Altera Logic Programmer + MasterBlaster/ByteBlasterMV |
| JTAG Boundary Scan | — | Not supported (classic MAX architecture) |
| Military/Avionics SMD | — | 5962-01-417-3750 (QML variant: EPM5064JM/883) |