EPM5128JC vs EPM5064JC-1 비교

다음의 상세 나란히 비교: EPM5128JC 제조: Altera 및 EPM5064JC-1 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5128JC EPM5064JC-1
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete NRND
재고 상태 In Stock In Stock
단가 (USD) $9.75 $18.25
Product Family MAX 5000 —
Device Type EPLD / CPLD EPLD (Erasable Programmable Logic Device)
Macrocell Count 128 —
Propagation Delay (tPD) 35 ns —
Logic Elements Programmable AND/OR/XOR array 128 (Logic Array Blocks)
Supply Voltage (VCC) 5 V (typical) 5 V nominal (4.75 V – 5.25 V)
핀 수 68 —
Package Type PLCC-68 (JLCC) ceramic, J-leaded —
Dedicated Inputs 8 [DATA_NEEDED: dedicated input count]
User I/O Pins [DATA_NEEDED: user I/O pin count] —
Configuration Memory UV-erasable EPROM (windowed package) —
Programming Interface Altera MAX+PLUS II / A+PLUS / legacy programmer —
동작 온도 Commercial 0C to +70C 0 °C to +70 °C (commercial, -JC suffix)
실장 유형 Surface Mount (PLCC socket or solder) Surface Mount (PLCC socket recommended)
Boundary Scan JTAG IEEE 1149.1 (family feature) —
Process Technology CMOS EPROM 0.8 µm CMOS
RoHS 상태 [DATA_NEEDED: RoHS status - legacy part] Non-compliant (windowed ceramic, contains Pb in glass frit)
Lead-Free [DATA_NEEDED: lead-free status] —
Family — MAX 5000
Macro Cells — 64
Usable Gates — 1250 (typical)
Maximum Operating Frequency — 33.3 MHz (fCNT)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: tPD typical/max in ns]
Programmable Pins — 36 (typical I/O, 44-pin PLCC)
패키지 — 44-pin PLCC (J-lead, windowed ceramic)
Erasure Method — UV-erasable through quartz window
Programming Method — Altera Logic Programmer + MasterBlaster/ByteBlasterMV
JTAG Boundary Scan — Not supported (classic MAX architecture)
Military/Avionics SMD — 5962-01-417-3750 (QML variant: EPM5064JM/883)

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