EPM5128JC vs EPM5064JC-1 对比
详细并排对比 EPM5128JC 出自 Altera 和 EPM5064JC-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5128JC | EPM5064JC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.75 | $18.25 |
| Product Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Logic Elements | Programmable AND/OR/XOR array | 128 (Logic Array Blocks) |
| Supply Voltage (VCC) | 5 V (typical) | 5 V nominal (4.75 V – 5.25 V) |
| 引脚数 | 68 | — |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | — |
| Dedicated Inputs | 8 | [DATA_NEEDED: dedicated input count] |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Configuration Memory | UV-erasable EPROM (windowed package) | — |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | — |
| 工作温度 | Commercial 0C to +70C | 0 °C to +70 °C (commercial, -JC suffix) |
| 安装类型 | Surface Mount (PLCC socket or solder) | Surface Mount (PLCC socket recommended) |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | — |
| Process Technology | CMOS EPROM | 0.8 µm CMOS |
| RoHS 状态 | [DATA_NEEDED: RoHS status - legacy part] | Non-compliant (windowed ceramic, contains Pb in glass frit) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 |
| Macro Cells | — | 64 |
| Usable Gates | — | 1250 (typical) |
| Maximum Operating Frequency | — | 33.3 MHz (fCNT) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD typical/max in ns] |
| Programmable Pins | — | 36 (typical I/O, 44-pin PLCC) |
| 封装 | — | 44-pin PLCC (J-lead, windowed ceramic) |
| Erasure Method | — | UV-erasable through quartz window |
| Programming Method | — | Altera Logic Programmer + MasterBlaster/ByteBlasterMV |
| JTAG Boundary Scan | — | Not supported (classic MAX architecture) |
| Military/Avionics SMD | — | 5962-01-417-3750 (QML variant: EPM5064JM/883) |