EPM5128JC vs EPM5064JC-1 比較

詳細な並列比較: EPM5128JC メーカー: Altera および EPM5064JC-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5128JC EPM5064JC-1
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete NRND
在庫状況 In Stock In Stock
単価(USD) $9.75 $18.25
Product Family MAX 5000 —
Device Type EPLD / CPLD EPLD (Erasable Programmable Logic Device)
Macrocell Count 128 —
Propagation Delay (tPD) 35 ns —
Logic Elements Programmable AND/OR/XOR array 128 (Logic Array Blocks)
Supply Voltage (VCC) 5 V (typical) 5 V nominal (4.75 V – 5.25 V)
ピン数 68 —
Package Type PLCC-68 (JLCC) ceramic, J-leaded —
Dedicated Inputs 8 [DATA_NEEDED: dedicated input count]
User I/O Pins [DATA_NEEDED: user I/O pin count] —
Configuration Memory UV-erasable EPROM (windowed package) —
Programming Interface Altera MAX+PLUS II / A+PLUS / legacy programmer —
動作温度 Commercial 0C to +70C 0 °C to +70 °C (commercial, -JC suffix)
実装タイプ Surface Mount (PLCC socket or solder) Surface Mount (PLCC socket recommended)
Boundary Scan JTAG IEEE 1149.1 (family feature) —
Process Technology CMOS EPROM 0.8 µm CMOS
RoHS ステータス [DATA_NEEDED: RoHS status - legacy part] Non-compliant (windowed ceramic, contains Pb in glass frit)
Lead-Free [DATA_NEEDED: lead-free status] —
Family — MAX 5000
Macro Cells — 64
Usable Gates — 1250 (typical)
Maximum Operating Frequency — 33.3 MHz (fCNT)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: tPD typical/max in ns]
Programmable Pins — 36 (typical I/O, 44-pin PLCC)
パッケージ — 44-pin PLCC (J-lead, windowed ceramic)
Erasure Method — UV-erasable through quartz window
Programming Method — Altera Logic Programmer + MasterBlaster/ByteBlasterMV
JTAG Boundary Scan — Not supported (classic MAX architecture)
Military/Avionics SMD — 5962-01-417-3750 (QML variant: EPM5064JM/883)

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