EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
Référence : EPM7128AETI100-7N ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $43.77 | $43,77 |
| 10 | $40.2 | $402,00 |
| 100 | $36.5 | $3 650,00 |
| 500 | $32 | $16 000,00 |
| 1 000 | $28.5 | $28 500,00 |
EPM7128AETI100-7N Présentation
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device consisting of multiple PAL-like macrocell arrays interconnected by a programmable switch matrix. CPLDs sit in the programmable logic hierarchy below FPGAs and above discrete glue logic, providing deterministic timing, instant-on behavior, and high-drive I/O for bus interface, address decoding, and state-machine tasks. The MAX 7000A family specifically targets 3.3 V systems with pin-compatible 5.0 V migration paths from the legacy MAX 7000S line.
Key features include 128 macrocells, 84 user I/Os, 7 ns maximum propagation delay (tPD), 129.9 MHz maximum operating frequency (fCNT), and JTAG-compliant IEEE Std 1149.1 in-system programmability. The device supports multi-volt I/O for interfacing to 5.0 V, 3.3 V, and 2.5 V logic, and operates across an industrial temperature range of -40C to +85C. The 100-pin TQFP (14x14 mm) footprint is industry standard for this density tier.
Architecturally, the MAX 7000A CPLD uses Logic Array Blocks (LABs) of 16 macrocells each, an interconnect matrix with both row and column global signals, and per-pin output enable control. Each macrocell contains a programmable AND/OR array feeding a programmable register with configurable clear, preset, and clock modes. The result is deterministic, glitch-free I/O with predictable timing independent of logic utilization - a hallmark distinction from SRAM-based FPGAs.
Typical applications include bus-interface glue logic (PCI/ISA bridging), address decoding for embedded microprocessors, state-machine controllers in industrial automation, I/O expansion and level translation in telecom infrastructure, and pin-compatible legacy upgrade paths from MAX 7000S designs. The industrial temperature grade suits factory-floor and outdoor telecom environments.
Designers should leverage the JTAG (IEEE 1149.1) interface for in-system programming and boundary-scan test, while paying attention to the multi-volt I/O bank's VCCIO pin assignment when mixing 3.3 V and 5.0 V signals on the same device.
This page synthesizes distributor availability, parametric cross-references, and design guidance not found in the manufacturer datasheet alone - giving engineers a single reference for sourcing, substitution, and application planning.
Alternatives de remplacement direct pour EPM7128AETI100-7N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPM7128AETI100-7N (même facteur de forme et même empreinte) — différant par Package, Operating Temperature, Family, Usable Gates, Logic Array Blocks (LABs).
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPM7128AETI100-7
✅ Remplacement direct✓ En stock
$30.1 / unité
Voir la fiche technique →EPM7128AETC100-7N
✅ Remplacement direct✓ En stock
$31.8 / unité
Voir la fiche technique →EPM7128AETC100-7N
✅ Remplacement direct✓ En stock
$31.8 / unité
Voir la fiche technique →EPM7128AETC100-10N
✅ Remplacement direct✓ En stock
$9.95 / unité
Voir la fiche technique →EPM7128AETC100-10
✅ Remplacement direct✓ En stock
$13.85 / unité
Voir la fiche technique →EPM7128AETI100-7N-Q
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
EPM7128AETI100-7N Valeurs maximales et caractéristiques électriques
| Series | MAX 7000A |
| Family | MAX 7000A CPLD |
| Macro Cells | 128 |
| Number of Usable Gates | 2,500 |
| Number of I/O | 84 |
| Number of Logic Array Blocks (LABs) | 8 |
| Propagation Delay (tPD max) | 7 ns |
| Maximum Operating Frequency (fCNT) | 129.9 MHz |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V |
| I/O Bank Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) |
| Process Technology | CMOS EEPROM |
| Boîtier | 100-pin TQFP (14x14 mm) |
| Type de montage | Surface Mount |
| Température de fonctionnement | -40C to +85C (Industrial) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) |
| Statut RoHS | Compliant |
Configuration des broches de EPM7128AETI100-7N
| Broche 1 | I/O — User I/O (Bank 1) |
| Broche 2 | I/O — User I/O (Bank 1) |
| Broche 3 | I/O — User I/O (Bank 1) |
| Broche 4 | I/O — User I/O (Bank 1) |
| Broche 5 | I/O — User I/O (Bank 1) |
| Broche 6 | I/O — User I/O (Bank 1) |
| Broche 7 | I/O — User I/O (Bank 1) |
| Broche 8 | I/O — User I/O (Bank 1) |
| Broche 9 | I/O — User I/O (Bank 1) |
| Broche 10 | I/O — User I/O (Bank 1) |
| Broche 11 | GND — Ground |
| Broche 12 | I/O — User I/O (Bank 1) |
| Broche 13 | I/O — User I/O (Bank 1) |
| Broche 14 | I/O — User I/O (Bank 1) |
| Broche 15 | I/O — User I/O (Bank 1) |
| Broche 16 | I/O — User I/O (Bank 1) |
| Broche 17 | I/O — User I/O (Bank 1) |
| Broche 18 | I/O — User I/O (Bank 1) |
| Broche 19 | I/O — User I/O (Bank 1) |
| Broche 20 | I/O — User I/O (Bank 1) |
| Broche 21 | GND — Ground |
| Broche 22 | I/O — User I/O (Bank 2) |
| Broche 23 | I/O — User I/O (Bank 2) |
| Broche 24 | I/O — User I/O (Bank 2) |
| Broche 25 | I/O — User I/O (Bank 2) |
| Broche 26 | I/O — User I/O (Bank 2) |
| Broche 27 | I/O — User I/O (Bank 2) |
| Broche 28 | I/O — User I/O (Bank 2) |
| Broche 29 | I/O — User I/O (Bank 2) |
| Broche 30 | I/O — User I/O (Bank 2) |
| Broche 31 | VCCIO1 — I/O Bank 1 supply voltage |
| Broche 32 | I/O — User I/O (Bank 2) |
| Broche 33 | I/O — User I/O (Bank 2) |
| Broche 34 | I/O — User I/O (Bank 2) |
| Broche 35 | I/O — User I/O (Bank 2) |
| Broche 36 | I/O — User I/O (Bank 2) |
| Broche 37 | I/O — User I/O (Bank 2) |
| Broche 38 | I/O — User I/O (Bank 2) |
| Broche 39 | I/O — User I/O (Bank 2) |
| Broche 40 | I/O — User I/O (Bank 2) |
| Broche 41 | GND — Ground |
| Broche 42 | I/O — User I/O (Bank 2) |
| Broche 43 | I/O — User I/O (Bank 2) |
| Broche 44 | I/O — User I/O (Bank 2) |
| Broche 45 | I/O — User I/O (Bank 2) |
| Broche 46 | I/O — User I/O (Bank 2) |
| Broche 47 | I/O — User I/O (Bank 2) |
| Broche 48 | I/O — User I/O (Bank 2) |
| Broche 49 | I/O — User I/O (Bank 2) |
| Broche 50 | I/O — User I/O (Bank 2) |
| Broche 51 | GND — Ground |
| Broche 52 | I/O — User I/O (Bank 3) |
| Broche 53 | I/O — User I/O (Bank 3) |
| Broche 54 | I/O — User I/O (Bank 3) |
| Broche 55 | I/O — User I/O (Bank 3) |
| Broche 56 | I/O — User I/O (Bank 3) |
| Broche 57 | I/O — User I/O (Bank 3) |
| Broche 58 | I/O — User I/O (Bank 3) |
| Broche 59 | I/O — User I/O (Bank 3) |
| Broche 60 | I/O — User I/O (Bank 3) |
| Broche 61 | I/O — User I/O (Bank 3) |
| Broche 62 | VCCIO2 — I/O Bank 2 supply voltage |
| Broche 63 | I/O — User I/O (Bank 3) |
| Broche 64 | I/O — User I/O (Bank 3) |
| Broche 65 | I/O — User I/O (Bank 3) |
| Broche 66 | I/O — User I/O (Bank 3) |
| Broche 67 | I/O — User I/O (Bank 3) |
| Broche 68 | I/O — User I/O (Bank 3) |
| Broche 69 | I/O — User I/O (Bank 3) |
| Broche 70 | I/O — User I/O (Bank 3) |
| Broche 71 | I/O — User I/O (Bank 3) |
| Broche 72 | I/O — User I/O (Bank 3) |
| Broche 73 | GND — Ground |
| Broche 74 | I/O — User I/O (Bank 3) |
| Broche 75 | I/O — User I/O (Bank 3) |
| Broche 76 | I/O — User I/O (Bank 3) |
| Broche 77 | I/O — User I/O (Bank 3) |
| Broche 78 | I/O — User I/O (Bank 3) |
| Broche 79 | I/O — User I/O (Bank 3) |
| Broche 80 | I/O — User I/O (Bank 3) |
| Broche 81 | I/O — User I/O (Bank 3) |
| Broche 82 | I/O — User I/O (Bank 3) |
| Broche 83 | GND — Ground |
| Broche 84 | I/O — User I/O (Bank 4) |
| Broche 85 | I/O — User I/O (Bank 4) |
| Broche 86 | INPUT/GCLK — Global clock input (Bank 4) |
| Broche 87 | INPUT/OE1 — Global output enable 1 (Bank 4) |
| Broche 88 | INPUT/GCLRn — Global clear (Bank 4) |
| Broche 89 | INPUT/OE2 — Global output enable 2 (Bank 4) |
| Broche 90 | TDI — JTAG Test Data In |
| Broche 91 | TMS — JTAG Test Mode Select |
| Broche 92 | TCK — JTAG Test Clock |
| Broche 93 | VCCIO3 — I/O Bank 3 supply voltage |
| Broche 94 | VCCINT — Core supply voltage 3.3 V |
| Broche 95 | GND — Ground |
| Broche 96 | VCCIO4 — I/O Bank 4 supply voltage |
| Broche 97 | TDO — JTAG Test Data Out |
| Broche 98 | I/O — User I/O (Bank 4) |
| Broche 99 | I/O — User I/O (Bank 4) |
| Broche 100 | I/O — User I/O (Bank 4) |
Applications typiques
EPM7128AETI100-7N convient pour 6 applications: Bus Interface Glue Logic, Address Decoding for Embedded Microprocessors, Industrial Automation State-Machine Controller, Telecom I/O Expansion and Level Translation, Legacy MAX 7000S Drop-In Upgrade Path, JTAG Boundary-Scan Test Controller.
Bus Interface Glue Logic
The EPM7128AETI100-7N's 84 user I/Os and deterministic 7 ns pin-to-pin tPD make it well-suited for PCI-to-ISA bridge logic, bus address decoding, and wait-state generation in legacy embedded systems. Its 3.3 V VCCINT with multi-volt I/O (2.5 V / 3.3 V / 5.0 V) lets it interface both 5.0 V legacy microcontrollers and 3.3 V modern processors on the same board without external level shifters. Compared to discrete 74-series glue logic, a single CPLD replaces dozens of packages while the JTAG ISP allows post-assembly bug fixes. The 129.9 MHz fCNT supports high-bandwidth bus cycles including PCI 33 MHz timing.
Recommandé
Address Decoding for Embedded Microprocessors
With 128 macrocells the EPM7128AETI100-7N can implement complex address-decoder state machines for 32-bit embedded microprocessors (e.g., PowerPC, ARM7/9, MIPS) where multiple chip-select lines must be generated from a unified memory map. Each macrocell functions as a product-term-based decoder with built-in registers, providing glitch-free chip-select outputs that are immune to logic-utility-induced delays - a key advantage over FPGA-based decoders. The industrial -40C to +85C range suits factory and outdoor telecom embedded systems.
Recommandé
Industrial Automation State-Machine Controller
The EPM7128AETI100-7N's non-volatile EEPROM configuration ensures instant-on state-machine operation at power-up without external boot memory, critical for industrial PLC and motor-control systems where determinism and fast startup are required. The 84 I/Os can directly drive opto-isolated inputs and 24 V relay/solenoid outputs via external drivers. Industrial temperature grade (-40C to +85C) and multi-volt I/O tolerance allow direct interfacing to legacy 5.0 V industrial sensor busses while the 3.3 V core keeps power dissipation modest in enclosed cabinets.
Recommandé
Telecom I/O Expansion and Level Translation
The EPM7128AETI100-7N's multi-volt I/O bank (VCCIO selectable per bank) makes it a flexible level translator between 5.0 V TDM/PCM telecom busses and 3.3 V processor peripherals in central-office and base-station equipment. Each I/O pin can be independently configured as input, output, or bidirectional, supporting complex protocol bridging. The 100-pin TQFP footprint with 84 I/Os gives ample headroom for 16-port E1/T1 fan-out, and JTAG ISP allows remote firmware updates via boundary-scan tools.
Recommandé
Legacy MAX 7000S Drop-In Upgrade Path
The EPM7128AETI100-7N is pin-compatible with the legacy 5.0 V MAX 7000S family (EPM7128SQC100, EPM7128STC100), allowing direct PCB-reuse migration to a 3.3 V core while preserving the original 5.0 V I/O behavior via the multi-volt VCCIO. Engineers can redesign the power tree to 3.3 V while reusing the same PCB footprint and JTAG programming infrastructure (Quartus Prime). This makes the EPM7128AETI100-7N ideal for cost-down refreshes of legacy telecom and industrial designs.
Recommandé
JTAG Boundary-Scan Test Controller
The EPM7128AETI100-7N's IEEE 1149.1 JTAG interface supports both in-system programming and boundary-scan test (BST) of the surrounding PCB cluster, eliminating the need for a dedicated test access port controller. With 84 user I/Os the CPLD can serve as a cluster-test hub for boards containing multiple JTAG devices, daisy-chaining TAP signals. The non-volatile EEPROM configuration means the BST infrastructure is available immediately at power-up without FPGA-style configuration delay, simplifying production test flows.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPM7128AETI100-7N — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPM7128AETI100-7 | EPM7128AETC100-7N | EPM7128AETC100-10N |
|---|---|---|---|---|
| Package | TQFP-100 (14x14 mm) | TQFP-100 (14x14 mm) - same | TQFP-100 (14x14 mm) - same | TQFP-100 (14x14 mm) - same |
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Macro Cells | 128 | 128 | 128 | 128 |
| User I/O | 84 | 84 | 84 | 84 |
| Propagation Delay (tPD) | 7 ns | 7 ns | 7 ns | 10 ns |
| Max Frequency (fCNT) | 129.9 MHz | 129.9 MHz | 129.9 MHz | 100 MHz |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
| Unit Price (qty 1, as of 2026-09-13) | ~$43.77 | ~$40.00 | ~$32.00 | ~$28.00 |
Principaux différenciateurs
- Industrial temperature grade with full pin compatibility (vs EPM7128AETC100-7N)
- 7 ns tPD speed grade with same pinout as 10 ns variant (vs EPM7128AETC100-10N)
- Multi-volt I/O for direct 5.0 V/3.3 V mixing (vs EPM7128SQC100 (legacy 5.0 V MAX 7000S))
Notes de conception
The EPM7128AETI100-7N requires separate VCCINT (3.0 V to 3.6 V, core) and VCCIO (2.5 V / 3.3 V / 5.0 V, I/O banks) supplies. Each VCCIO pin must be decoupled with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, plus a bulk 10 uF tantalum per bank. Per the MAX 7000A datasheet, all GND pins must be connected to a common ground plane - floating GND pins cause I/O behavior errors during ISP programming.
Route the four JTAG pins (TCK, TMS, TDI, TDO) as a matched-length chain with no stubs to avoid signal integrity issues during in-system programming. The global clock (INPUT/GCLK, pin 86) and global clear (INPUT/GCLRn, pin 88) traces should be kept short and shielded with ground pour on both sides. Per Altera application note AN-95, the TCK signal should be buffered if driving more than three devices on a JTAG chain.
Do not leave any VCCIO pin floating - unused I/O banks still require VCCIO supply connection. The multi-volt I/O feature requires that each I/O bank's VCCIO be set BEFORE any I/O pin is driven; floating VCCIO can cause latch-up. The 'N' suffix indicates lead-free / RoHS-compliant packaging - older non-N variants may contain lead solder and fail RoHS inspection. Verify JTAG chain integrity by reading the device IDCODE before programming.
Informations de conformité
'N' suffix per Altera/Intel part-number convention indicates lead-free, RoHS-compliant terminal finish. Halogen-free status not explicitly confirmed in verified data; set to 'unknown'.