EPM7128SLC84-7N vs EPM7128SLC8410 Comparaison
Comparaison détaillée côte à côte de EPM7128SLC84-7N par Intel et EPM7128SLC8410 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM7128SLC84-7N | EPM7128SLC8410 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,75 | $9,75 |
| Series | MAX 7000S | — |
| Programmable Type | In System Programmable (ISP) | — |
| Type de mémoire | EEPROM | — |
| Number of Macrocells | 128 | — |
| Number of Logic Elements/Blocks | 8 (Logic Array Blocks) | — |
| Number of Usable Gates | 2,500 | — |
| Number of I/O Pins | 68 | — |
| Propagation Delay (tpd) Max | 7.5 ns | — |
| Maximum Operating Frequency | 125 MHz | 125 MHz (counter) |
| Counter Speed (Internal) | up to 175.4 MHz (family max) | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Température de fonctionnement | 0 C to +70 C (Commercial) | 0C to +70C (commercial) |
| Boîtier | 84-LCC (J-Lead), PLCC-84 | 84-pin PLCC (J-lead) |
| Type de montage | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Statut RoHS | Compliant (lead-free 'N' suffix) | [DATA_NEEDED: RoHS status - not stated in verified data] |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Family | — | MAX 7000S |
| Macrocells | — | 128 |
| Logic Elements / Gates | — | 2500 usable gates |
| User I/O Pins | — | 68 |
| Number of Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tPD) | — | 10 ns |
| Setup Time (tSU) | — | 7 ns |
| I/O Voltage (MultiVolt) | — | 2.5 V / 3.3 V / 5.0 V |
| Program Memory Type | — | EEPROM (in-system programmable) |
| JTAG Support | — | IEEE Std 1149.1 boundary-scan |