EPM7128SLC84-10 - 128-Macrocell MAX 7000 CPLD | Intel
Référence : EPM7128SLC8410 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.85 | $1 385,00 |
| 500 | $11.4 | $5 700,00 |
| 1 000 | $9.75 | $9 750,00 |
EPM7128SLC8410 Présentation
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single chip, connected through a central programmable interconnect matrix. CPLDs sit in the programmable logic hierarchy between discrete PALs/GALs and larger FPGAs: they offer deterministic timing (typically predictable propagation delays), instant-on configuration from on-chip EEPROM, and moderate logic densities (hundreds of macrocells vs. millions of LUTs in modern FPGAs). The MAX 7000 family was Altera's second-generation MAX architecture and became the de-facto standard for glue-logic integration, bus interfacing, and state-machine consolidation in industrial and telecom designs from the mid-1990s through the 2000s.
Key specifications include 128 macrocells (each containing a programmable AND/OR array plus one flip-flop), a maximum operating frequency of approximately 125 MHz for counter operation, a tPD (pin-to-pin delay) of 10 ns, and a tSU (setup time) of 7 ns. The device operates from a single 5.0 V supply (VCCINT = 4.75-5.25 V) with MultiVolt I/O supporting 2.5 V, 3.3 V, or 5.0 V mixed-voltage interfacing. The 84-pin PLCC package exposes 68 usable I/O plus JTAG and configuration pins.
Internally, the MAX 7000S architecture uses four Logic Array Blocks (LABs) interconnected by a continuous programmable interconnect array (PIA). Each LAB contains 16 macrocells; each macrocell combines a programmable AND array, an OR/Exclusive-OR gate, a programmable flip-flop, and selectable clear/preset/clock control. Programming data is stored in on-chip EEPROM cells, allowing the device to retain its configuration indefinitely without external memory. The -10 speed grade indicates a 10 ns propagation delay.
Typical applications include bus-interface bridging (e.g., 8/16/32-bit MCU-to-peripheral glue logic), address decoding and chip-select generation, state-machine consolidation in industrial controllers, and 5 V system glue logic in legacy telecom and factory-automation equipment. The -10 grade is the slowest of the three speed grades offered in this package (-7, -10, -15) and is therefore preferred when propagation delay is not timing-critical.
When designing with this part, note that 84-pin PLCC sockets are widely available but require through-hole PCB footprint - plan for socket cost and assembly labor. Designers migrating legacy 5 V designs to 3.3 V MCUs often choose the MAX 7000S as the voltage-translation bridge because of its MultiVolt pinout.
This page synthesizes distributor pricing, drop-in alternatives drawn from the MAX 7000S family, and practical design notes not found in the manufacturer datasheet.
Alternatives de remplacement direct pour EPM7128SLC8410 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPM7128SLC8410 (même facteur de forme et même empreinte) — différant par Mounting Type, RoHS Status, Package, Family, Propagation Delay (tPD).
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPM7128SLC84-15
✅ Remplacement direct✓ En stock
$10.4 / unité
Voir la fiche technique →EPM7128SLC84-7N
✅ Remplacement direct✓ En stock
$8.75 / unité
Voir la fiche technique →EPM7128SLC84-7N
✅ Remplacement direct✓ En stock
$8.75 / unité
Voir la fiche technique →EPM7128SLC84-6N
✅ Remplacement direct✓ En stock
$8.75 / unité
Voir la fiche technique →EPM7128AELC84-10N
✅ Remplacement direct✓ En stock
$10.45 / unité
Voir la fiche technique →EPM7128ELC84-10
✅ Remplacement direct✓ En stock
$7.2 / unité
Voir la fiche technique →EPM7128ELC84-12
✅ Remplacement direct✓ En stock
$10.4 / unité
Voir la fiche technique →EPM7128ELC84-20
✅ Remplacement direct✓ En stock
$24.2 / unité
Voir la fiche technique →EPM7128SLC8410 Valeurs maximales et caractéristiques électriques
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX 7000S |
| Macrocells | 128 |
| Logic Elements / Gates | 2500 usable gates |
| User I/O Pins | 68 |
| Number of Logic Array Blocks (LABs) | 8 |
| Propagation Delay (tPD) | 10 ns |
| Setup Time (tSU) | 7 ns |
| Maximum Operating Frequency | 125 MHz (counter) |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Voltage (MultiVolt) | 2.5 V / 3.3 V / 5.0 V |
| Program Memory Type | EEPROM (in-system programmable) |
| JTAG Support | IEEE Std 1149.1 boundary-scan |
| Boîtier | 84-pin PLCC (J-lead) |
| Température de fonctionnement | 0C to +70C (commercial) |
| Type de montage | Surface Mount (PLCC socket or direct solder) |
Configuration des broches de EPM7128SLC8410
| Broche 1 | I/O — User I/O pin (macrocell-driven bidirectional) |
| Broche 2 | I/O — User I/O pin |
| Broche 3 | I/O — User I/O pin |
| Broche 4 | I/O — User I/O pin |
| Broche 5 | I/O — User I/O pin |
| Broche 6 | I/O — User I/O pin |
| Broche 7 | I/O — User I/O pin |
| Broche 8 | I/O — User I/O pin |
| Broche 9 | I/O — User I/O pin |
| Broche 10 | I/O — User I/O pin |
| Broche 11 | GND — Ground |
| Broche 12 | I/O — User I/O pin |
| Broche 13 | I/O — User I/O pin |
| Broche 14 | I/O — User I/O pin |
| Broche 15 | I/O — User I/O pin |
| Broche 16 | I/O — User I/O pin |
| Broche 17 | I/O — User I/O pin |
| Broche 18 | I/O — User I/O pin |
| Broche 19 | I/O — User I/O pin |
| Broche 20 | I/O — User I/O pin |
| Broche 21 | VCC — 5.0 V supply (VCCINT) |
| Broche 22 | I/O — User I/O pin |
| Broche 23 | I/O — User I/O pin |
| Broche 24 | I/O — User I/O pin |
| Broche 25 | I/O — User I/O pin |
| Broche 26 | I/O — User I/O pin |
| Broche 27 | I/O — User I/O pin |
| Broche 28 | I/O — User I/O pin |
| Broche 29 | I/O — User I/O pin |
| Broche 30 | I/O — User I/O pin |
| Broche 31 | GND — Ground |
| Broche 32 | I/O — User I/O pin |
| Broche 33 | I/O — User I/O pin |
| Broche 34 | I/O — User I/O pin |
| Broche 35 | I/O — User I/O pin |
| Broche 36 | I/O — User I/O pin |
| Broche 37 | I/O — User I/O pin |
| Broche 38 | I/O — User I/O pin |
| Broche 39 | I/O — User I/O pin |
| Broche 40 | I/O — User I/O pin |
| Broche 41 | VCC — 5.0 V supply (VCCINT) |
| Broche 42 | I/O — User I/O pin |
| Broche 43 | I/O — User I/O pin |
| Broche 44 | I/O — User I/O pin |
| Broche 45 | I/O — User I/O pin |
| Broche 46 | I/O — User I/O pin |
| Broche 47 | I/O — User I/O pin |
| Broche 48 | I/O — User I/O pin |
| Broche 49 | I/O — User I/O pin |
| Broche 50 | I/O — User I/O pin |
| Broche 51 | GND — Ground |
| Broche 52 | I/O — User I/O pin |
| Broche 53 | I/O — User I/O pin |
| Broche 54 | I/O — User I/O pin |
| Broche 55 | I/O — User I/O pin |
| Broche 56 | I/O — User I/O pin |
| Broche 57 | I/O — User I/O pin |
| Broche 58 | I/O — User I/O pin |
| Broche 59 | I/O — User I/O pin |
| Broche 60 | I/O — User I/O pin |
| Broche 61 | VCC — 5.0 V supply (VCCINT) |
| Broche 62 | I/O — User I/O pin |
| Broche 63 | I/O — User I/O pin |
| Broche 64 | I/O — User I/O pin |
| Broche 65 | I/O — User I/O pin |
| Broche 66 | I/O — User I/O pin |
| Broche 67 | I/O — User I/O pin |
| Broche 68 | I/O — User I/O pin |
| Broche 69 | I/O — User I/O pin |
| Broche 70 | I/O — User I/O pin |
| Broche 71 | GND — Ground |
| Broche 72 | I/O — User I/O pin |
| Broche 73 | I/O — User I/O pin |
| Broche 74 | I/O — User I/O pin |
| Broche 75 | I/O — User I/O pin |
| Broche 76 | I/O — User I/O pin |
| Broche 77 | I/O — User I/O pin |
| Broche 78 | I/O — User I/O pin |
| Broche 79 | I/O — User I/O pin |
| Broche 80 | I/O — User I/O pin |
| Broche 81 | VCC — 5.0 V supply (VCCINT) |
| Broche 82 | TDI — JTAG Test Data In |
| Broche 83 | TMS — JTAG Test Mode Select |
| Broche 84 | TCK — JTAG Test Clock |
Applications typiques
EPM7128SLC8410 convient pour 6 applications: 5 V System Glue Logic / Bus Interface Bridge, Address Decoding and Chip-Select Generation, Legacy Telecom Backplane Glue Logic, State-Machine Consolidation in Industrial Controllers, Legacy ISA / PC/104 Expansion Card Glue, 5 V MCU-to-FPGA Bridge / Logic Translator.
5 V System Glue Logic / Bus Interface Bridge
The EPM7128SLC84-10 is widely deployed as 5 V glue logic in industrial controllers and telecom backplane designs where multiple microprocessors, peripherals, and memory devices require address decoding, chip-select generation, and wait-state insertion. With 128 macrocells and 68 user I/O pins, it can replace 4-8 discrete 22V10 or 16V8 PALs on a single board. The MAX 7000S family's MultiVolt I/O (2.5/3.3/5.0 V) allows direct connection to a 3.3 V MCU and 5 V peripherals from the same chip, eliminating level-translator ICs. The 10 ns tPD keeps propagation delay below 50 ns for cascaded decode chains, which is acceptable for ISA-bus, PC/104, and VME timing budgets. Designers should reserve one LAB (16 macrocells) per major decode region and use the OE pins for output enable control of bus transceivers.
Recommandé
Address Decoding and Chip-Select Generation
In 8/16/32-bit microcontroller designs the EPM7128SLC84-10 is often used to decode the full address bus into multiple peripheral chip-selects, replacing discrete 'HC138 or 'HC139 decoders with a single reprogrammable device. With 128 macrocells and the LAB-based AND/OR architecture, the designer can implement complex multi-input decode equations (e.g., A23:A16 with /RD, /WR qualifiers) in a single device. The 10 ns tPD adds 10 ns of address-to-CS delay versus discrete logic, which is usually within the bus-access budget for 25 MHz MCUs. The JTAG interface enables in-system reprogramming of decode maps, eliminating jumper changes during firmware bring-up. Per MAX 7000S datasheet pinout, GCLK1 and GCLK2 pins can also serve as global clock inputs for synchronous chip-select timing.
Recommandé
Legacy Telecom Backplane Glue Logic
The EPM7128SLC84-10 became a de-facto standard for 5 V telecom backplane designs in the late 1990s, where it consolidates bus-arbiter logic, watchdog timers, and H.110/CT-bus time-slot switching into a single device. With 2500 usable gates and 68 I/O pins it can handle the parallel bus interfaces of multiple E1/T1 framer ICs plus their interrupt-aggregation logic. The 84-pin PLCC package is socketable for field-replaceable maintenance - a key requirement for central-office hardware that must be serviced without desoldering. The 10 ns tPD suits the 8 MHz bus-cycle timing of legacy TDM buses. Modern redesigns migrate to MAX V or MachXO2 in TQFP packages, but installed-base EPM7128SLC84-10 systems continue to ship spare parts.
Recommandé
State-Machine Consolidation in Industrial Controllers
Industrial PLC and motion-controller designers use the EPM7128SLC84-10 to consolidate discrete 74HC74-based state machines into a single reprogrammable device, simplifying board layout and improving testability. The MAX 7000S family's macrocell flip-flops (one per macrocell, 128 total) can implement complex multi-state FSMs with Moore or Mealy outputs at clock rates up to 125 MHz. Each LAB has dedicated clock, clear, and preset signals; per the datasheet, GCLK1 and GCLK2 serve as global synchronous clocks across all 8 LABs, ensuring deterministic timing regardless of placement. The 84-pin PLCC's socketed form factor simplifies field replacement when firmware bugs are patched via JTAG. The 5 V core makes it compatible with industrial 24 V-conditioned power rails without level shifters.
Recommandé
Legacy ISA / PC/104 Expansion Card Glue
The EPM7128SLC84-10 was a popular choice for ISA-bus and PC/104 expansion cards in the 1990s and 2000s, integrating address decode, bus-buffer direction control, and interrupt-acknowledge logic in one chip. The 68 user I/O pins are sufficient for 16-bit ISA address decode plus 8-bit data-buffer control, and the 10 ns tPD meets the 8 MHz ISA timing budget. Designers can map custom I/O addresses via JTAG without re-spinning the PCB - critical for low-volume industrial cards where mask changes are cost-prohibitive. MultiVolt I/O allows the 5 V CPLD to drive both 5 V ISA slots and 3.3 V peripherals on the same card. The 84-pin PLCC socket simplifies card rework in field-deployed systems. New designs should migrate to MAX V CPLDs in TQFP packages since the EPM7128SLC84-10 is now obsolete.
Recommandé
5 V MCU-to-FPGA Bridge / Logic Translator
Modern designs often pair a legacy 5 V microcontroller with a 1.8/3.3 V FPGA, and the EPM7128SLC84-10 serves as the voltage-translation and protocol-conversion bridge. With MultiVolt I/O, the CPLD can simultaneously interface its 5 V core side to the MCU and its 3.3 V I/O bank to the FPGA, eliminating external level-shifters. The 128 macrocells can implement custom hand-shake protocols, FIFO flag logic, and interrupt aggregation between mismatched voltage domains. The 10 ns tPD adds minimal latency to high-speed serial or parallel handshakes. The MAX 7000S datasheet confirms the device operates reliably at industrial -40C to +85C (for industrial-grade variants) and offers JTAG-controlled I/O voltage selection per pin, providing fine-grained voltage-domain control.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPM7128SLC8410 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPM7128SLC84-15 | EPM7128SLC84-7 | EPM7128SLC84-7N | EPM7128SLC84-6N | EPM7128ELC84-10 |
|---|---|---|---|---|---|---|
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000E |
| Propagation Delay (tPD) | 10 ns | 15 ns | 7 ns | 7 ns | 6 ns | 10 ns |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/O Pins | 68 | 68 | 68 | 68 | 68 | 68 |
| VCCINT (Core) | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete (lead-free) | Obsolete (lead-free) | Obsolete |
Principaux différenciateurs
- Best balance of speed and cost in the MAX 7000S family (vs EPM7128SLC84-15 vs EPM7128SLC84-7)
- Pinout-identical to all MAX 7000S 84-pin PLCC speed grades (vs EPM7128SLC84-7, -10, -15, -7N, -6N)
- 5 V VCCINT is fully compatible with MAX 7000E (non-S) family in same package (vs EPM7128ELC84-10)
Notes de conception
The EPM7128SLC84-10 operates from a single 5.0 V VCCINT supply, but the I/O banks support MultiVolt operation at 2.5 V, 3.3 V, or 5.0 V via separate VCCIO pins. Per the MAX 7000S datasheet, all four VCC pins (21, 41, 61, 81) must be decoupled with 0.1 uF ceramic capacitors placed within 5 mm of the package, plus a 10 uF bulk capacitor per VCC pin. Failure to provide adequate decoupling causes VCC glitches during simultaneous switching outputs (SSO) that can corrupt the EEPROM configuration. Decoupling is especially critical during JTAG programming when the I/O buffers switch at high di/dt.
The 84-pin PLCC package has J-leads on a 1.27 mm (50 mil) pitch with a 30.35 mm (1.195 inch) body. PLCC sockets are widely available and strongly recommended for development and field-replaceable designs - soldering PLCC directly to the PCB complicates rework. If direct soldering, ensure the land pattern follows IPC-7351 PLCC guidelines with adequate thermal relief for hand-rework. Per the datasheet, all four corner pins (1, 21, 41, 84 area) and central GND pins must be connected with low-impedance traces.
Do not confuse the MAX 7000S (5 V VCCINT, 'S' suffix) with the MAX 7000AE (3.3 V VCCINT, 'AE' suffix) when substituting - the VCCINT voltage is different and cross-family substitution without re-designing the power supply will damage the device. The EPM7128AELC84-10N is a 3.3 V variant in the same PLCC package but is NOT a drop-in replacement for 5 V designs. Verify VCCINT in the datasheet before substituting any 'AE' or 'E' suffix variant.
JTAG signals TDI, TMS, TCK, and TDO should be routed with 50 ohm controlled impedance if JTAG chain length exceeds 100 mm, and terminated near the CPLD with 10-22 kohm pull-ups on TMS, TDI, and TCK per the IEEE 1149.1 standard. Place JTAG test points at the board edge for in-system programming access without disassembling the chassis. The TCK signal is the most sensitive to noise; keep it away from switching I/O traces and clock signals to avoid false JTAG state transitions.
Informations de conformité
RoHS / REACH / lead-free status not specified in the verified data. Lead-free N-suffix variants (ePM7128SLC84-7N, ePM7128SLC84-6N) were released by Altera/Intel specifically for lead-free compliance - prefer these for new designs requiring RoHS. The non-N parts may be SnPb finish (legacy).
