EPM9320ARI208-10 vs EPM9320ARI208-10N Comparaison
Comparaison détaillée côte à côte de EPM9320ARI208-10 par Intel et EPM9320ARI208-10N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N ObsoleteComparaison des spécifications
| Paramètre | EPM9320ARI208-10 | EPM9320ARI208-10N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $27,20 | $16,20 |
| Programmable Type | In System Programmable (ISP) | — |
| Number of Macrocells | 320 | — |
| Number of Logic Elements/Blocks | 20 | — |
| Number of Gates | 6000 | — |
| Number of I/O | 132 | — |
| Propagation Delay tpd(1) Max | 10 ns | — |
| Maximum Counter Frequency | 144.9 MHz | — |
| Voltage Supply - Internal | 4.5 V to 5.5 V | — |
| Température de fonctionnement | -40 C to +85 C (TA) | -40 C to +85 C (industrial) |
| Type de montage | Surface Mount | Surface Mount |
| Boîtier / Format | 208-BFQFP Exposed Pad | — |
| Supplier Device Package | 208-RQFP | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 | — |
| Product Status | Obsolete | — |
| Packaging | Tray | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Family | — | MAX 9000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 6,000 |
| Macrocells | — | 320 |
| Logic Array Blocks (LABs) | — | 20 |
| Maximum Operating Frequency | — | 144.9 MHz |
| Propagation Delay (tPD) | — | 10 ns (speed grade -10) |
| Tension d'alimentation | — | 4.5 V to 5.5 V |
| Boîtier | — | 208-pin RQFP (S-PQFP-G208) |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-system (ISP) via IEEE 1149.1 JTAG |
| Global Dedicated Inputs | — | 16 |
| Architecture | — | Multiple Array MatriX (MAX) third-generation |