EPM9560RC304-2 vs EPM9560RCRC304-15 Comparaison
Comparaison détaillée côte à côte de EPM9560RC304-2 par Intel et EPM9560RCRC304-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM9560RC304-2 - MAX 9000 EPLD 12k Gates 304-pin RQFP | Intel / Altera
EPM9560RC304-2 ObsoleteComparaison des spécifications
| Paramètre | EPM9560RC304-2 | EPM9560RCRC304-15 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $55,00 | $0,00 |
| Family | MAX 9000 | — |
| Device Type | CPLD (EPLD - Erasable PLD) | — |
| Usable Gates | Approximately 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 | [DATA_NEEDED: LAB count] |
| Macrocells | [DATA_NEEDED: macrocell count] | — |
| User I/O Pins | 304 | — |
| Boîtier | 304-pin RQFP (RC) | 304-pin RQFP (PowerQuad Flat Pack) |
| Speed Grade | -2 | — |
| Core Supply Voltage | 5.0 V | — |
| I/O Supply Voltage | 5.0 V | — |
| Programming Technology | EEPROM (in-system programmable) | — |
| JTAG Support | IEEE Std. 1149.1 (boundary-scan + ISP) | — |
| Température de fonctionnement | Commercial (0C to +70C) | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | Third-generation Multiple Array MatriX (MAX) |
| Configuration Memory | On-chip EEPROM (non-volatile) | EEPROM (non-volatile, in-system programmable) |
| Device Family | — | MAX 9000 (EPM9560) |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Frequency | — | 117.6 MHz |
| Tension d'alimentation | — | 5.0 V |
| In-System Programmability (ISP) | — | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 (built-in) |
| Plage de température de fonctionnement | — | [DATA_NEEDED: operating temperature range] |
| Number of User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Lead Finish | — | [DATA_NEEDED: lead finish] |