EPM9560RC304-2 vs EPM9560RCRC304-15 对比

详细并排对比 EPM9560RC304-2 出自 Intel 和 EPM9560RCRC304-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC304-2 EPM9560RCRC304-15
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $55.00 $0.00
Family MAX 9000 —
Device Type CPLD (EPLD - Erasable PLD) —
Usable Gates Approximately 12,000 12,000
Logic Array Blocks (LABs) 16 [DATA_NEEDED: LAB count]
Macrocells [DATA_NEEDED: macrocell count] —
User I/O Pins 304 —
封装 304-pin RQFP (RC) 304-pin RQFP (PowerQuad Flat Pack)
Speed Grade -2 —
Core Supply Voltage 5.0 V —
I/O Supply Voltage 5.0 V —
Programming Technology EEPROM (in-system programmable) —
JTAG Support IEEE Std. 1149.1 (boundary-scan + ISP) —
工作温度 Commercial (0C to +70C) —
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Architecture Multiple Array MatriX (MAX) - third generation Third-generation Multiple Array MatriX (MAX)
Configuration Memory On-chip EEPROM (non-volatile) EEPROM (non-volatile, in-system programmable)
Device Family — MAX 9000 (EPM9560)
Logic Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Macro Cells — 560
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Maximum Frequency — 117.6 MHz
电源电压 — 5.0 V
In-System Programmability (ISP) — Yes, via IEEE Std. 1149.1 JTAG
JTAG Interface — IEEE Std. 1149.1 (built-in)
工作温度范围 — [DATA_NEEDED: operating temperature range]
Number of User I/O Pins — [DATA_NEEDED: user I/O pin count]
Lead Finish — [DATA_NEEDED: lead finish]

数据手册与资源

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