EPM9560RC304-2 vs EPM9560RCRC304-15 Comparison
Detailed side-by-side comparison of EPM9560RC304-2 by Intel and EPM9560RCRC304-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RC304-2 - MAX 9000 EPLD 12k Gates 304-pin RQFP | Intel / Altera
EPM9560RC304-2 ObsoleteSpecification Comparison
| Parameter | EPM9560RC304-2 | EPM9560RCRC304-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $55.00 | $0.00 |
| Family | MAX 9000 | β |
| Device Type | CPLD (EPLD - Erasable PLD) | β |
| Usable Gates | Approximately 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 | [DATA_NEEDED: LAB count] |
| Macrocells | [DATA_NEEDED: macrocell count] | β |
| User I/O Pins | 304 | β |
| Package | 304-pin RQFP (RC) | 304-pin RQFP (PowerQuad Flat Pack) |
| Speed Grade | -2 | β |
| Core Supply Voltage | 5.0 V | β |
| I/O Supply Voltage | 5.0 V | β |
| Programming Technology | EEPROM (in-system programmable) | β |
| JTAG Support | IEEE Std. 1149.1 (boundary-scan + ISP) | β |
| Operating Temperature | Commercial (0C to +70C) | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Architecture | Multiple Array MatriX (MAX) - third generation | Third-generation Multiple Array MatriX (MAX) |
| Configuration Memory | On-chip EEPROM (non-volatile) | EEPROM (non-volatile, in-system programmable) |
| Device Family | β | MAX 9000 (EPM9560) |
| Logic Type | β | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | β | 560 |
| Pin-to-Pin Propagation Delay (tPD) | β | 15 ns |
| Maximum Frequency | β | 117.6 MHz |
| Supply Voltage | β | 5.0 V |
| In-System Programmability (ISP) | β | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | β | IEEE Std. 1149.1 (built-in) |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |
| Number of User I/O Pins | β | [DATA_NEEDED: user I/O pin count] |
| Lead Finish | β | [DATA_NEEDED: lead finish] |