EPM9560RC304-2 vs EPM9560RCRC304-15 Comparison

Detailed side-by-side comparison of EPM9560RC304-2 by Intel and EPM9560RCRC304-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC304-2 EPM9560RCRC304-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 9000 —
Device Type CPLD (EPLD - Erasable PLD) —
Usable Gates Approximately 12,000 12,000
Logic Array Blocks (LABs) 16 [DATA_NEEDED: LAB count]
Macrocells [DATA_NEEDED: macrocell count] —
User I/O Pins 304 —
Package 304-pin RQFP (RC) 304-pin RQFP (PowerQuad Flat Pack)
Speed Grade -2 —
Core Supply Voltage 5.0 V —
I/O Supply Voltage 5.0 V —
Programming Technology EEPROM (in-system programmable) —
JTAG Support IEEE Std. 1149.1 (boundary-scan + ISP) —
Operating Temperature Commercial (0C to +70C) —
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Architecture Multiple Array MatriX (MAX) - third generation Third-generation Multiple Array MatriX (MAX)
Configuration Memory On-chip EEPROM (non-volatile) EEPROM (non-volatile, in-system programmable)
Device Family — MAX 9000 (EPM9560)
Logic Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Macro Cells — 560
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Maximum Frequency — 117.6 MHz
Supply Voltage — 5.0 V
In-System Programmability (ISP) — Yes, via IEEE Std. 1149.1 JTAG
JTAG Interface — IEEE Std. 1149.1 (built-in)
Operating Temperature Range — [DATA_NEEDED: operating temperature range]
Number of User I/O Pins — [DATA_NEEDED: user I/O pin count]
Lead Finish — [DATA_NEEDED: lead finish]

Datasheets & Resources

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