K4S641632K-UC75 vs K4S641632H-UC75 Comparaison
Comparaison détaillée côte à côte de K4S641632K-UC75 par Samsung Electro-Mechanics et K4S641632H-UC75 par Samsung Electronics. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Samsung Electro-Mechanics
K4S641632K-UC75 - 64Mb SDRAM 4Mx16 3.3V 54-TSOP II | Samsung
K4S641632K-UC75 ✓ ActifSamsung Electronics
K4S641632H-UC75 - 64Mb H-die SDRAM 1M x 16 x 4 Banks | Samsung
K4S641632H-UC75 ObsoleteComparaison des spécifications
| Paramètre | K4S641632K-UC75 | K4S641632H-UC75 |
|---|---|---|
| Marque | Samsung Electro-Mechanics | Samsung Electronics |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Actif | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,92 | $2,85 |
| Type de mémoire | Synchronous DRAM (SDR SDRAM) | SDRAM (Synchronous DRAM) |
| Density | 64 Mbit (67,108,864 bits) | 64 Mb (67,108,864 bits) |
| Organisation de la mémoire | 4 banks x 1,048,576 words x 16 bits (4Mx16) | 1M x 16 bits x 4 Banks |
| Supply Voltage (VDD/VDDQ) | 3.3 V +/- 0.3 V | 3.3 V |
| Speed Grade | UC75 (133 MHz, CAS Latency 3, tCK = 7.5 ns) | — |
| Fréquence d'horloge maximale | 133 MHz | — |
| CAS Latency (CL) | 2 or 3 (programmable) | — |
| Burst Length | 1, 2, 4, 8 or full page | 1, 2, 4, 8, Full Page |
| Refresh Cycles | 4096 (64 ms refresh interval) | — |
| Number of Banks | 4 | — |
| Address Multiplexing | Row: 12 bits, Column: 8 bits | Yes (RAS#, CAS# controlled) |
| Interface | 16-bit data bus, LVTTL-compatible | LVCMOS |
| Température de fonctionnement | 0 C to +70 C (Commercial) | 0C to +70C (Commercial) |
| Boîtier | 54-pin TSOP-II | — |
| Package Outline | 10.16 mm x 22.22 mm, 0.8 mm pitch | — |
| Type de montage | Surface Mount (Tape & Reel) | — |
| Process Technology | Samsung high-performance CMOS | Samsung high-performance CMOS |
| Statut RoHS | Compliant | — |
| Clock Frequency | — | 133 MHz |
| Max Operating Current | — | 135 mA |
| Package Type | — | 54-pin TSOP-II |
| Lead Finish | — | Pb-Free (RoHS compliant) |
| Bank Architecture | — | 4 Banks |
| Burst Type | — | Sequential or Interleave |
| Refresh | — | Auto-Refresh and Self-Refresh |
| Data Width | — | 16 bits |