P1013NXN2LFB vs P1022NXN2LFB Comparaison
Comparaison détaillée côte à côte de P1013NXN2LFB par NXP Semiconductors et P1022NXN2LFB par NXP Semiconductors. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
NXP Semiconductors
P1013NXN2LFB - QorIQ P1022 Power Arch SoC 1GHz | NXP
P1013NXN2LFB ⚠ Dernier achatNXP Semiconductors
P1022NXN2LFB - QorIQ Dual-Core 1.067 GHz SoC | NXP | Networking
P1022NXN2LFB ⚠ Dernier achatComparaison des spécifications
| Paramètre | P1013NXN2LFB | P1022NXN2LFB |
|---|---|---|
| Marque | NXP Semiconductors | NXP Semiconductors |
| Catégorie | Microcontrollers | Microcontrollers |
| Statut du cycle de vie | Dernier achat | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $32,85 | $78,40 |
| Family | QorIQ P1022 (P1 series) | — |
| Core Architecture | 32-bit Power Architecture e500v2 | — |
| Number of Cores | 1 | — |
| Core Frequency | 1.067 GHz | — |
| L1 Cache (per core) | 32 KB instruction + 32 KB data | — |
| L2 Cache | 256 KB platform cache | — |
| Memory Controller | DDR2/DDR3 with ECC, 64-bit data bus | DDR2/DDR3 with ECC support, up to 32-bit |
| Ethernet MACs | 3 x 10/100/1000 (2x SGMII/HS SerDes, 1x RGMII) | 3 x 10/100/1000 Mbps Gigabit |
| PCI Express | 2 x PCIe Gen 1.1 (x4 / x1) | — |
| USB | 1 x USB 2.0 with integrated PHY | USB 2.0 host/device |
| Other Interfaces | eSDHC, eSPI, I2C, UART, eLBC, LCD controller | — |
| Boîtier | 689-ball TEPBGA II (31 mm x 31 mm) | — |
| Température de fonctionnement | -40C to +125C (junction) | -40 °C to +125 °C (industrial) |
| Process | 45 nm SOI | — |
| Tension d'alimentation | 1.5 V / 1.8 V / 2.5 V / 3.3 V | 3.13 V to 3.47 V |
| Security | SEC 4.0 (optional crypto accelerator) on die variant | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA, requires thermal via array under die) |
| Statut RoHS | Compliant (Pb-free ball finish) | — |
| Architecture | — | Power Architecture e500 dual-core (RISC, 32-bit) |
| Clock Speed (Core) | — | 1.067 GHz |
| Platform Version | — | 1067/533/667 ET NE r1.1 |
| Core Count | — | 2 |
| Package Type | — | TEPBGA-689 (Plastic, halogen-free, RoHS-compliant) |
| Package Dimensions | — | 31 x 31 mm, 2.23 mm height |
| Nombre de broches | — | 689 |
| PCIe Interfaces | — | 3 x PCIe Gen1 |
| Display Controller | — | 32-bit LCD controller |
| Security Engine | — | Integrated (symmetric/asymmetric crypto acceleration) |
| RoHS Compliance | — | Yes (halogen-free) |