P1013NXN2LFB vs P1022NXN2LFB Vergleich
Detaillierter Direktvergleich von P1013NXN2LFB von NXP Semiconductors und P1022NXN2LFB von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
NXP Semiconductors
P1013NXN2LFB - QorIQ P1022 Power Arch SoC 1GHz | NXP
P1013NXN2LFB ⚠ Letzte BestellmöglichkeitNXP Semiconductors
P1022NXN2LFB - QorIQ Dual-Core 1.067 GHz SoC | NXP | Networking
P1022NXN2LFB ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | P1013NXN2LFB | P1022NXN2LFB |
|---|---|---|
| Marke | NXP Semiconductors | NXP Semiconductors |
| Kategorie | Microcontrollers | Microcontrollers |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $32,85 | $78,40 |
| Family | QorIQ P1022 (P1 series) | — |
| Core Architecture | 32-bit Power Architecture e500v2 | — |
| Number of Cores | 1 | — |
| Core Frequency | 1.067 GHz | — |
| L1 Cache (per core) | 32 KB instruction + 32 KB data | — |
| L2 Cache | 256 KB platform cache | — |
| Memory Controller | DDR2/DDR3 with ECC, 64-bit data bus | DDR2/DDR3 with ECC support, up to 32-bit |
| Ethernet MACs | 3 x 10/100/1000 (2x SGMII/HS SerDes, 1x RGMII) | 3 x 10/100/1000 Mbps Gigabit |
| PCI Express | 2 x PCIe Gen 1.1 (x4 / x1) | — |
| USB | 1 x USB 2.0 with integrated PHY | USB 2.0 host/device |
| Other Interfaces | eSDHC, eSPI, I2C, UART, eLBC, LCD controller | — |
| Gehäuse | 689-ball TEPBGA II (31 mm x 31 mm) | — |
| Betriebstemperatur | -40C to +125C (junction) | -40 °C to +125 °C (industrial) |
| Process | 45 nm SOI | — |
| Versorgungsspannung | 1.5 V / 1.8 V / 2.5 V / 3.3 V | 3.13 V to 3.47 V |
| Security | SEC 4.0 (optional crypto accelerator) on die variant | — |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA, requires thermal via array under die) |
| RoHS-Status | Compliant (Pb-free ball finish) | — |
| Architecture | — | Power Architecture e500 dual-core (RISC, 32-bit) |
| Clock Speed (Core) | — | 1.067 GHz |
| Platform Version | — | 1067/533/667 ET NE r1.1 |
| Core Count | — | 2 |
| Package Type | — | TEPBGA-689 (Plastic, halogen-free, RoHS-compliant) |
| Package Dimensions | — | 31 x 31 mm, 2.23 mm height |
| Pin-Anzahl | — | 689 |
| PCIe Interfaces | — | 3 x PCIe Gen1 |
| Display Controller | — | 32-bit LCD controller |
| Security Engine | — | Integrated (symmetric/asymmetric crypto acceleration) |
| RoHS Compliance | — | Yes (halogen-free) |